Importance and Role of wire in high speed chips

1. The wire
Dr. Sachin Pable
Matoshri College of Engineering and
Research Centre

2. Integrated Circuits
Basic Components
Active devices Interconnects
Local (short)
interconnect
Global (Long)
interconnect

3. VLSI Interconnects
 Used to connect components on a VLSI chip
 Used to connect chips on a multichip module
 Used to connect multichip modules on a system
board

4. Wires on chip
• Most of the chip is covered by
wires, many layers of wires
• Transistors: little things under wires
• Wires as important as transistors
Affect:
 Speed
 Power
 Noise
• Alternating layers usually run
orthogonally
Most of chip is wires
(interconnect)

5. • In past history of integrated circuits, on-chip interconnect
wires were considered to be second class citizens.
• only to be considered in special cases or when performing
high-precision analysis.
• With the progress semiconductor technologies, this picture is
undergoing rapid changes.

6. 85% 15%
50% 50%
20% 80%
Mid 1980’s
Gate delay dominates,
Mid 90
Gate delay and wire
delay
Today
Mostly wire delay

7. Figure 4.4: Breakdown of (a) delay and (b) energy
in simulation of FPGA at 0.4V subthreshold voltage
[7].

8. Why Al
• Low cost, easily purified
• Low resistivity
• Good adherence to Si and SiO2
• Good patternability
• Ease of deposition

9. The wiring forms a complex geometry that introduces
parasitics: resistive, capacitive and inductive.
All three have multiple effects on the circuit behavior.
 An increase in propagation delay, or, equivalently, a
drop in performance.
 An impact on the energy dissipation and the power
distribution.
 An introduction of extra noise sources, which affects
the reliability of the circuit.

10. Problem with Al
• Device Dimension Decreased
Current Density Increases
Decreased reliability
(Electronics, shorting between level of Al
Solution
• Alternative Metal/ Metal Composite – Cu is preffered
in modern process- CNT will prefer in future

11. Metallic Interconnections Issues
Parasitic Capacitances and Inductances
 Reduction of Propagation Delays
 Reduction of Crosstalk Effects
 Reduction of Electromigration-Induced Failure

12. CMOS inverter driving interconnect
The delay for RC Cu
interconnect driven by a
CMOS driver is given by
[129],
l)C.RC.R(
lC.R4.0)CC(R
loadWWdriv
2
WWloaddrivdrivd



13. Interconnect scaling trends
Ideal scaling Constant dimension
Line width/spacing S 1
Wire thickness S 1
Interlevel dielectric S 1
Wire length 1/sqrt(S) 1/sqrt(S)
Resistance/unit length 1/S2 1
Capacitance/unit length 1 1
RC delay 1/S3 1/S
Current density 1/S S

14. Technology scaling and wire

16. • Pitch= w + s
• Aspect Ratio,
AR=t/w
Modern process have
AR=2 for short
AR=3 for long
interconnect
Ground
Ground
W
S
H
t
Wire geometry
l
w s
t
h

17. Wire_Resistance
• The resistance of a wire is proportional to its length L
and inversely proportional to its cross-section A.
HW
L
A
L
R


H
R
W
L
RR






18. Wire capacitance
1. Area component ( Also referred to as parallel plate
capacitance components)
2. Fringing field component
3. Wire- to-wire capacitance components
To improve delay
 Increase dielectric thickness
 Reduce wire width
 Reduce spacing

19. 1. Parallel plate capacitance
For w >> tdi (thickness of insulating material) it is
assumed that the electrical field lines are orthogonal
to the capacitance plates.
WL
t
C
di
di
int

20. Fringing capacitance
• In modern process W/H ratio drops down
significantly.
• It causes capacitance between side walls of
wire and substrate, called fringing capacitance.
• It can no longer be ignored.
2/,
)/log(
2.
HWwwhere
Htt
w
CCC
di
di
di
di
fringppWire




21. Capacitance as function of W and tdi
@From Schaper83
W/tdi indirectly W/H

22. Inter wire capacitance
• Interlayer capacitance is
more dominant in multilayer
structure. This effect is more
pronounce for wires in the
higher interconnect layers.

23. Propagation Delays
Definitions
Delay Time
• Time required by the output signal (current or
voltage) to reach 50% of its steady state value
Rise Time
• Time required by the output signal to rise from 10%
to 90% of its steady state value
Propagation Time
• Time required by the output signal to reach 90% of its
steady state value

24. 24
The Lumped Model
Vout
Driver
cwire
Vin
Clumped
Rdriver
Vout
Paracitics of wires are distributed along its length.
But, when signle paracitic components is dominant
it is oftenly useful to consider lumped model.
For small resistive components, low to medium
frequency range only capacitance component can be
considered.
Distributed capacitance can be lumped into single
capacitor.

25. The Lumped RC-Model
The Elmore Delay
To model propagation delay
time along a path from the
source s to destination i
considering the loading effect
of the other nodes on the path
from s to k
The shared path resistance Rik
s
The Elmore delay

26. Elmore delay

27. 27
RC-Models

28. • Wires are a distributed system
– Approximate with lumped element models
 3-segment p-model is accurate to 3% in simulation
 L-model needs 100 segments for same accuracy!
C
R
C/N
R/N
C/N
R/N
C/N
R/N
C/N
R/N
R
C
L-model
R
C/2 C/2
R/2 R/2
C
N segments
-model T-model

29. 29
Driving an RC-line
V
in
Rs Vout
(rw,cw,L)

30. 30
Design Rules of Thumb
 rc delays should only be considered when tpRC >>
tpgate of the driving gate
Lcrit >>  tpgate/0.38rc
 rc delays should only be considered when the rise
(fall) time at the line input is smaller than RC, the
rise (fall) time of the line
trise < RC
otherwise, the change in the input signal is slower than
the propagation delay of the wire

31. • Capacitance as function of AR
1 1.5 2 2.5 3
400
500
600
700
800
900
1000
Aspect Ratio
Capacitance(fF)
Opt.mixed CNT bundle
Mixed CNT bundle [94]
Cu
L=5000um 50
100
150
200
250
300
48 72 96 120 144
Spacing (nm)
Driverandtotaldelay(ns) 8
16
24
32
40
Interconnectdelay(ns)
Total delay Driver delay Inter.delay
Delay as function of spacing

32. PDP as function of interconnect length
2
4
6
8
10
0
10
20
30
40
0
10
20
30
40
50
60
Interconnect length
(mm)1 x min. driver width
PDP(fJ)
Superthreshold regime
Subthreshold regime

33. Delay as function of interconnect width
40
60
80
100
120
0
5
10
15
20
10
0
10
1
10
2
10
3
Interconnect width (nm)
Min. X driver size
Delay(ns)
Conv. device and interconnect
Opt. device and interconnect
40
60
80
100
120
0
5
10
15
20
10
-1
10
0
10
1
10
2
Interconnect width (nm)Minimum X driver size
PDP(J)
Conv. interconnect and device
Opt. interconnect and device

34. Interconnect Techniques
Cin Cpar. Cload
InterconnectDriver Receiver
Cpar.
InterconnectTapered Driver Tapered Receiver
CloadCin
(a)
(b)
©
Driver Receiver
Interconnect Interconnect Interconnect
Repeater RepeaterCin Clo
ad
Driver Sizing
Tapered Driver
Repeater Insertion
34

35. Repeaters
 R and C are proportional to l
 RC delay is proportional to l2
Unacceptably great for long wires
 Break long wires into N shorter segments
Drive each one with an inverter or buffer
Wire Length: l
Driver Receiver
l/N
Driver
Segment
Repeater
l/N
Repeater
l/N
ReceiverRepeater
NSegments

36. Interconnect Slide 36
Repeater Design
• How many repeaters should we use?
• How large should each one be?
• Equivalent Circuit
– Wire length l
• Wire Capacitance Cw*l, Resistance Rw*l
– Inverter width W (nMOS = W, pMOS = 2W)
• Gate Capacitance C’*W, Resistance R/W
R/W
C'WCw
l/2N Cw
l/2N
Rw
lN

37. Effect of repeater insertion

38. Crosstalk
• The crosstalk coupling represents the parasitic
transient voltage induced by a switching interconnect
on a neighboring interconnect.
• Crosstalk is the interference in a victim line signal
transmission caused by switching activity on
aggressor lines
• As integration density of on chip interconnect
increases at every technology node, the crosstalk
effect becomes more pronounced [132].
• Strongly depends on the value of the coupling
capacitance (Cc), transition-time skew and the
adjacent interconnect length

39. • In order to keep crosstalk minimum, the capacitance
between two wires should not be too large [27].
• This is feasible by breaking a long interconnect by
inserting intermediate buffers.
• Another approach of reducing the crosstalk is to use
shielding wires.
Crosstalk

40. Aggressor 1
CloadCw
Rw Lw
Cc
Rw Lw
Cw Cload
Rw Lw
Cw Cload
Aggressor 2
Victim Cc
Figure 5.19: Schematic of equivalent circuit
to model crosstalk between adjacent wires.
layer n+1
layer n
layer n-1
Cadj
Ctop
Cbot
ws
t
h1
h2

41. Crosstalk noise
• Crosstalk causes noise on nonswitching wires
• If victim is floating:
– model as capacitive voltage divider
adj
victim aggressor
gnd v adj
C
V V
C C
  

Cadj
Cgnd-v
Aggressor
Victim
Vaggressor
Vvictim

42. Driven Victims
• Usually victim is driven by a gate that fights noise
– Noise depends on relative resistances
– Victim driver is in linear region, agg. in saturation
– If sizes are same, Raggressor = 2-4 x Rvictim
1
1
adj
victim aggressor
gnd v adj
C
V V
C C k
  
 
 
 
aggressor gnd a adjaggressor
victim victim gnd v adj
R C C
k
R C C





 

Cadj
Cgnd-v
Aggressor
Victim
Vaggressor
Vvictim
Raggressor
Rvictim
Cgnd-a

43. Figure: Snapshot of signal transition due to
aggressor transitions for Cu interconnect.

44. Snapshots of voltages across victim wire
due to aggressors transitions.

45. 5. Effect of Crosstalk on Interconnect Performance
Aggressor
Transition
Victim
Transition
Rise
Time
(ns)
Fall Time
(ns)
Delay
(ns)
PDP (fJ)
RLC Power
(nW)
Without
Aggressors
Low to high 256.7 285.2 270.9 60.64 17.35
High to low 242.2 286.14 264.2 59.16 15.9
Low to high Low to high 256.7 285.2 270.98 60.64 17.35
High to low High to low 242.2 286.14 264.2 59.16 15.9
Low to high High to low 394.9 380 387.9 110.2 25.58
High to low Low to high 257 479 368.4 104.88 22.66
Low to high Held at low Results in rise glitch on victim
High to low Held at low Results in undershoot on victim
Table : Effect of crosstalk on interconnect performance (L=10 mm).
45

46. Future interconnects

47. Classification of CNTs
MWCNT
Dmax
Dmin
SWCNT
d
Mixed CNT
Bundle
(a) (b) (c)
Figure (a) Single-wall carbon nanotubes, (b) Multi-wall carbon nanotubes
and (c) Mixed CNT bundle
47
Carbon Nanotubes (CNTs)

48. Single-Wall Carbon Nanotubes (SWCNT)
 SWCNT: Single sheet of cylindrically rolled graphene
: diameter in nanometer range
 Depending upon rolling (chiralities) it produces either
metallic CNT or semiconducting CNT.
y
d
SWCNT
Ground Plane
4CQ
CE
(Rc+RQ)/2R/2(Rc+RQ)/2 R/2 L/2L/2
48
Fig. Equivalent RLC circuit of
SWCNT

49. SWCNT_ Resistance
• The resistance of a SWCNT (RCNT) consists of
 Quantum resistance (RQ) / an intrinsic resistance
 Contact resistance (RC). (20 to 120 kΩ [94])
 k5.6e4/hR 2
Q
For longer length, SWCNT resistance depends on its length
and applied voltage.
 k5.6e4/hR 2
CNT CNTl
)/(/  CNT
2
CNT le4hR CNTl
49
)/( 0CNTQCCNT ll1RRR Distributed resistance model of SWCNT:

50. SWCNT_Capacitance
• Capacitance of an isolated SWCNT is contributed by
 Electrostatic capacitance (CE)
With diameter ‘d’ placed at a distance ‘y’ away from a ground plane
 Quantum capacitance (CQ)
CQ of individual SWCNT has a typical value of 100 aF/μm.
The effective SWCNT capacitance is given by series
combination of CE and CQ
(y/d)nl
2
CE


f
2
Q hVe2C /
50

51. Mixed CNT Bundle
 Higher resistance associated with individual SWCNT
motivated researchers to use a bundle of CNTs.
 Theoretically, CNT bundles may contain only SWCNTs
or only MWCNTs.
 A mixed bundle consists of SWCNTs with a diameter
‘d’ and MWCNTs with various diameters (Din < di < Dout).
 Mixed CNT bundle is more realistic than SWCNT and
MWCNT bundle.
51

52. Thank you