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1. Peripheral Component Interconnect
(PCI).

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3. Dual Independent Bus (DIB)
 Backside Bus simultan
 Frontside Bus
 PCI Local Bus
 Menggunakan bridge
untuk tersambung ke
FSB

4. Perbandingan Bus
Bus Type Bus Bus MB/sec
Width Speed
ISA 16 bits 8 MHz 16 MBps
EISA 32 bits 8 MHz 32 MBps
VL-bus 32 bits 25 MHz 100 MBps
VL-bus 32 bits 33 MHz 132 MBps
PCI 32 bits 33 MHz 132 MBps
PCI 64 bits 33 MHz 264 MBps
PCI 64 bits 66 MHz 512 MBps
PCI 64 bits 133 MHz 1 GBps

5. North / South bridge

6. Contoh

8. PCI Card
A typical PCI card
PCI card – 47 pins

10. Pengantar : Operasi PCI Bus
Istilah
 Initiator
— Disebut juga Master
— Mengendalikan (owns) bus dan menginisiasi transfer data
— Setiap Initiator adalah juga Target
 Target
— Disebut Juga Slave
— Target dari transfer data (read or write)
 Agent
— Initiator atau Target pada PCI bus

11. Master-Slave

12. Pengantar : Operasi PCI Bus
PCI Bus Clock
 Semua aksi disinkronisasi oleh clock PCI
 Clock dapat berada di 0 MHz - 33 MHz dan semua perangkat PCI harus
mampu mendukung pada kisaran tersebut
 Spesifikasi revisi 2.1 memiliki kecepatan s/d 66 MHz
Address phase
 Pada waktu bersamaan identifier initiator menetapkan target device dand
tipe transaksi
 Initiator mengirimkan (assert) sinyal FRAME#
 Setiap target PCI akan mengunci (latch ) alamat dan mendecode

13. Pengantar : Operasi PCI Bus
Data Phase
 Jumlah byte data yang akan dikirimkan ditentukan oleh jumlah
sinyal enable Command/Byte Enable yang dikirimkan oleh
initiator
 initiator dan target harus siap untuk menyelesaikan proses data
phase
 Digunakan sinyal IRDY# and TRDY#
Transaction Duration
 Dengan mengirimkan sinyal FRAME# pada saat start address
phase and tetap sampai akhir data phase

14. Pengantar : Operasi PCI Bus
Transaction completion and return of bus to idle state
 Dengan cara deasserting sinyal FRAME# tetapi asserting IRDY#
 Ketika data transfer berakhit initiator mengembalikan the PCI bus
pada status idle state cara deasserting IRDY#

17. PCI Signals
 - Clock and Reset
 Transaction Control
1. Initiator Signals
2. Target Signals
3. Configuration Signals
 Address and Data Signals
 Arbitration Signals
 Error Signals

18. PCI Lines

19. Clock and Reset
 CLK
 — PCI input clock
 — All signals sampled on rising edge
 — 33MHz is really 33.33333MHz (30ns clk. period)
 — The clock is allowed to vary from 0 to 33 MHz
 – The frequency can change ―on the fly‖
 – Because of this, no PLLs are allowed
 RST#
 — Asynchronous reset
 — PCI device must tri-state all I/Os during reset

20. Transaction Control
Target Signals
 TRDY# – I/O
 — “T-Ready”
 — When the target asserts this signal, it tells the
initiator that it is ready to send or receive data
 STOP# – I/O
 — Used by target to indicate that it needs to
terminate the
 transaction

21. Transaction Control
Target Signals
 DEVSEL# – I/O
 — Device select
 — Part of PCI’s distributed address decoding
 – Each target is responsible for decoding the address
associated with each transaction
 – When a target recognizes its address, it asserts
DEVSEL# to claim the corresponding transaction

22. Transaction Control
Initiator Signals
 FRAME# – I/O
 — Signals the start and end of a transaction
 IRDY# – I/O
 — “I-Ready”
 — Assertion by initiator indicates that it is ready to
send receive data

23. Transaction Control
Configuration Signals
 Uses the same signals as the target, plus . . .
 IDSEL – I
 — “ID-Sel”
 — Individual device select for configuration – one
unique IDSEL line per agent
 — Solves the “chicken-and-egg” problem
 – Allows the system host to configure agents before
these agents know the PCI addresses to which they
must respond

24. Address and Data Signals
 AD[31:0] – I/O
 — 32-bit address/data bus
 — PCI is little endian (lowest numeric index is LSB)
 C/BE#[3:0] – I/O
 — 4-bit command/byte enable bus
 — Defines the PCI command during address phase
 — Indicates byte enable during data phases
 – Each bit corresponds to a ―byte-lane‖ in AD[31:0] – for
example,C/BE#[0] is the byte enable for AD[7:0]

25. C/BE[3:0]# Command Types
0000 Interrupt Acknowledge
0001 Special Cycle
0010 I/O Read
0011 I/O Write
0100 Reserved
0101 Reserved
0110 Memory Read
0111 Memory Write
1000 Reserved
1001 Reserved
1010 Configuration Read
1011 Configuration Write
1100 Memory Read Multiple
1101 Dual Address Cycle
1110 Memory Read Line
1111 Memory Write and Invalidate

26. Address and Data Signals
 PAR – I/O
 — Parity bit
 — Used to verify correct transmittal of address/data
and command/byte-enable
 — The XOR of AD[31:0], C/BE#[3:0], and PAR
should return zero (even parity)
 – In other words, the number of 1’s across these 37
signals should be even

27. Arbitration Signals
 For initiators only!
 REQ# – O
 — Asserted by initiator to request bus ownership
 — Point-to-point connection to arbiter – each initiator has its
own REQ# line
 GNT# – I
 — Asserted by system arbiter to grant bus ownership to the
initiator
 — Point-to-point connection from arbiter – each initiator has
its own GNT# line

28. PCI Bus Arbitration
• Arbiter
– Round
Robin
– Priority
– Two Level
Priority

29. Error Signals
 PERR# – I/O
 — Indicates that a data parity error has occurred
 — An agent that can report parity errors can have its
PERR# turned off during PCI configuration
 SERR# – I/O
 — Indicates a serious system error has occurred
 – Example: Address parity error
 — May invoke NMI (non-maskable interrupt, i.e., a
restart) in some systems

30. Operasi Bus Dasar
Terms
 Doubleword
— 32 bits, most often known as a “DWORD”
 Quadword
— 64 bits, sometimes known as a “QWORD”
 Burst transaction
— Any transaction consisting of more than one data phase
 Idle state (no bus activity)
— Indicated by FRAME# and IRDY# deasserted

31. Transfer Modes

32. Example #1 – Basic Write
 A four-DWORD burst from an initiator to a
target

33. Write Transfer

34. PCI Bus Cycles

35. Basic Write Transaction

36. Write Example – Things to Note
 The initiator has a phase profile of 3-1-1-1
 — First data can be transferred in three clock cycles
(idle + address +data = “3”)
 — The 2 nd , 3 rd , and last data are transferred one
cycle each (“1-1-1”)

37. Write Example – Things to Note
 The target profile is 5-1-1-1
 — Medium decode – DEVSEL# asserted on 2 nd clock after
FRAME#
 — One clock period of latency (or wait state) in the beginning
of the transfer
 – DEVSEL# asserted on clock 3, but TRDY# not asserted
unti clock 4
 — Ideal target write is 3-1-1-1
 Total of 4 data phases, but required 8 clocks
 — Only 50% efficiency

38. Target Address Decoding
 PCI uses distributed address decoding
 — A transaction begins over the PCI bus
 — Each potential target on the bus decodes the
transaction’s PCI address to determine whether it
belongs to that target’s assigned address space
 – One target may be assigned a larger address space
than another, and would thus respond to more addresses
 — The target that owns the PCI address then claims
the transaction by asserting DEVSEL#

39. Distributed Address Decoding

40. Target Decode
• Address decoders come in different speeds
• If a transaction goes unclaimed (nobody asserts
DEVSEL#), “Master Abort” occurs

41. Example #2 – Target Read
• A four-DWORD burst read from a target by an initiator

43. More Terms
 Turnaround cycle
 — “Dead” bus cycle to prevent bus contention
 Wait state
 — A bus cycle where it is possible to transfer data, but no
data
 transfer occurs
 — Target deasserts TRDY# to signal it is not ready
 — Initiator deasserts IRDY# to signal it is not ready
 Target termination
 — Target asserts STOP# to indicate that it needs to
terminate the current transaction

44. Target Read – Things to Note
 Wait states may be inserted dynamically by
the initiator or target by deasserting IRDY# or
TRDY#
 Either agent may signal the end of a
transaction
 — The target signals termination by asserting
STOP#
 — The initiator signals completion by deasserting
FRAME#

45. Zero and One Wait State
 A one-wait-state agent inserts a wait state at
the beginning of each data phase
 — This is done if an agent – built in older, slower
silicon – needs to pipeline critical paths internally
 — Reduces bandwidth by 50%

46. Bus Bandwidths

47. PCI-X 2.0 Write - Example

48. PCIe (PCI Express)
• Diperkenalkan tahun 2002, oleh Microsoft,
Dell, IBM, dan Intel.
• Bekerja pada 2.5GHz
dengan hanya
menggunakan 0.8V
• Backward compatible
dengan PCI

50. Perbedaan PCIe dengan PCI
• throughput meningkat 1056MBytes/sec dari
528MBytes/sec
• Komunikasi data : Serial (PCIe), Paralel (PCI)
• PCIe : Layered Architecture (Header)
• PCIe mempermudah proses timing yang rumit
dari spesifikasi PCI 64/66, sehingga membuat
PCIe lebih mudah didesain
• PCIe Mendukung hingga 4 slot pada 66MHz
sedangkan PCI 66 hanya mampu 3 slot : 2 slots
100MHz dan 1 slot 133MHz

51. Perbedaan PCIe dengan PCI (2)
• PCIe meningkatkan efisiensi bus dan
mengatasi kekurangan pada protokol PCI
Kekurangan PCI
– Shared bus bandwidth
– tidak mampu beroperasi pada aplikasi isochronous
– manajemen power yang terbatas
– relatif mahal untuk membuat parallel bus
– ukuran dan jumlah Connector
– masalah routing pada Board

54. Physical Layer
Fungsi Logika Physical Layer :
• Encoding/decoding dan scrambling
• Reset, initialization, multi-lane de-skew
• Speed, link width, lane mapping
Fungsi Elektrik Physical Layer
• Transmitter/Receiver
• Packet Exchange
• Power Management
• Polarity Reversal

55. Data Link Layer
Fungsi Data Link Layer
• Link management
• Error detection and reporting
• Packet storage for retry/replay
Data Link Layer Packets
• Link Data Integrity
• Sequencing
• CRC
• ACK/NACK
• Flow Control

56. Flow Control
PCI
• Arbitration, continuous retry, disconnect
• menghabiskan bandwidth dan power
• Compound PCI-to-PCI Bridges akan
menimbulkan masalah
PCI Express
• Credit-based flow control
• Ditangani seluruhnya oleh data link layer
• Tidak ada pengulangan (retries)
• Bandwidth yang besar

57. Transaction Layer
Fungsi Transaction Layer
• Data transactions
• Flow control management
Paket Transaction Layer
• Request/Completion Model
• Memory Read/Write
• I/O Read/Write
• Configuration Read/Write
• Messages

58. Formasi Paket

60. PCIe 2.0
 PCI-SIG announced the availability of the PCI
Express Base 2.0 specification on 15 January
2007. PCIe 2.0 doubles the bus standard's
bandwidth from 2.5 Gbit/s to 5 Gbit/s, meaning
a x32 connector can transfer data at up to
16 GB/s in each direction.
 PCIe 2.0 is completely backwards compatible
with PCIe v1.x. Graphic cards and motherboards
designed for v2.0 will be able to work with v1.1
and v1.0, and vice versa

61. PCIe 3.0
 In August 2007 PCI-SIG announced that PCI
Express 3.0 will carry a bit rate of 8
gigatransfers per second. The spec will be
backwards-compatible with existing PCIe
implementations and a final spec is due in 2009.
New features for PCIe 3.0 specification include a
number of optimizations for enhanced signaling
and data integrity, including transmitter and
receiver equalization, PLL improvements, clock
data recovery, and channel enhancements for
currently supported topologies