Bus Structure, Memory and I/O Interfacing Decoder 74LS138 Binary Decoder Address Decoding using 3 * 8 Decoder in 8085 microprocessor

1. D E C O D E R
7 4 L S 1 3 8 B I N A R Y D E C O D E R
A D D R E S S D E C O D I N G U S I N G 3 * 8 D E C O D E R
I N 8 0 8 5 M I C R O P R O C E S S O R
Bus Structure, Memory and I/O
Interfacing
Er. Sulav Paudel | MSc

2. Decoder
 The decoder is a logic circuit that indentifies each
combination of the signals present at its input.
 If the input to the decoder had ‘n’ lines, the decoder
will have 2n output lines.
 Eg, if n = 2, the no. of output lines = 2n = 22 = 4.
 The two lines can assume four combinations of input
signals – 00, 01, 10, 11; with each combination
identified by the output lines 0 to 3. If the input is 11,
the output line 3 will be at logic 1 and other will
remain at logic 0. This is called decoding.
Er. Sulav Paudel | MSc

3. Decoder
 Various types of decoders are available, eg., 3 to 8, 4
to 16, etc.
 In general decoders have enable lines too. The
decoder will not function unless enable lines are
activated.
A 2-to-4 Binary Decoders
Er. Sulav Paudel | MSc

4. 74LS138 Binary Decoder
 If the input has three binary lines, then the output
lines would be 8.
74LS138 Binary Decoder
Er. Sulav Paudel | MSc

5. 74LS138 Binary Decoder (cont.)
Er. Sulav Paudel | MSc
 74LS138 can be used to decode 3 address lines to enable
up to 8 memory chips (each of its output can be used to
enable a different chip).
 All 8 outputs are not asserted when the enable input is
not asserted.
 Only one output is asserted when enable input is
asserted, and the output asserted depends on the A, B, C
selection inputs (one output for each possible
combination).
 Sometimes an external logic gate may be used in
conjunction with the 74LS138 to perform decoding using
more than 3 address lines.

6. A 4-to-16 Binary Decoder Configuration
Er. Sulav Paudel | MSc

7. Memory Address Decoding
Er. Sulav Paudel | MSc

8. Memory Address Decoding
 The binary decoder requires only 3 address lines, (A0 to
A2) to select each one of the 8 chips (the lower part of the
address), while the remaining 8 address lines (A3 to A10)
select the correct memory location on that chip (the
upper part of the address).
 Having selected a memory location using the address
bus, the information at the particular internal memory
location is sent to a common “Data Bus” for use by the
microprocessor.
 This is of course a simple example but the principals
remain the same the same for all types of memory chips
or modules.
Er. Sulav Paudel | MSc

9. Encoder
 The encoder is a logic circuit that provides the
appropriate code (binary, BCD, etc.) as output for
each input signals.
 The process is reverse of decoding.
Er. Sulav Paudel | MSc

10. Address Decoding using 3 * 8 Decoder in 8085
Microprocessor
Interface 2K bytes of memory to 8085 with memory
address 8000H. (Using logic gates and decoder)
 Solution:
2K = 2048 = 211
The total address lines required will be A10 to A0.
Write the 8000H, starting addressing in the table
below. The ending address can be found as follows:
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1
Er. Sulav Paudel | MSc

11.  In this state, 11 bits are used for 2K bytes of memory.
 It will be minimum value when A10 to A0 lines are
zero and when A10 to A0 lines all are high, it will be
maximum value. So maximum value in HEX is
87FFH which is the ending address.
Er. Sulav Paudel | MSc

12. Address decoding using simple NAND gate
decoder
 Thus A15 to A11 = ‘1 0 0 0 0’, these lines are used to
select the memory chip.
Er. Sulav Paudel | MSc
Addressing decoding using simple NAND gate decoder

13. Address decoding using simple NAND gate 3 * 8
Decoder in 8085 Microprocessor
Er. Sulav Paudel | MSc

14. Address Decoding using 74LS138 Decoder
Er. Sulav Paudel | MSc
 Interface 64K (eight 8K * 8 bits) byte block of
memory with the physical address in the range
F0000H to FFFFFH
 Solution:
8K = 213 bytes in each EPROM

15. Address Decoding using 74LS138 Decoder
Er. Sulav Paudel | MSc
Mapped the memory directly to an 8K byte block
1st block: F0000H – F1FFFH
2nd block: F2000H – F3FFFH
3rd block: F4000H – F5FFFH
4th block: F6000H – F7FFFH
5th block: F8000H – F9FFFH
6th block: FA000H – FBFFFH
7th block: FC000H – FDFFFH
8th block: FE000H – FFFFFH

16. Address Decoding using 74LS138 Decoder
Er. Sulav Paudel | MSc
 The most significant hexadecimal digit must be F to
address the 8 EPROMS.
 Hence, address lines A16 – A19 may be used to
enable the 138 decoder (so that CE signals are only
generated if A16 – A19 are all asserted)

17. Address Decoding using 74LS138 Decoder
Er. Sulav Paudel | MSc
1st block: F0000 – F1FFFH = 1111 0000 0000 0000 0000
1111 0001 1111 1111 1111
2nd block: F2000 – F3FFFH
3rd block:
4th block:
5th block:
6th block:
7th block:
8th block: FE000 – FFFFFH = 1111 1110 0000 0000 0000
1111 1111 1111 1111 1111
Used for
Enable
pins
Used for
Selection
pins

18. Address Decoding using 74LS138 Decoder
Er. Sulav Paudel | MSc
 The address pins of each EPROM (Memory) must be
connected to the 13 least significant address lines in
order to address the 213 (=8K) bytes in each EPROM.