8086 pin diagram description


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It illustrates the pin diagram of 8086 microprocessor..

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8086 pin diagram description

  1. 1. 8086 pin diagram description8086 Pin diagram And ExplanationThe 8086 can operate in two modes these are theminimum mode and maximum mode .Forminimum mode, a unique processor system with asingle 8086 and for Maximum mode a multiprocessor system with more than one 8086.MN/MX- is an input pin used to select one of thismode .when MN/MX is high the 8086 operatesin minimum mode .In this mode the 8086 isconfigured to support small single processor
  2. 2. system using a few devices that the system bus.when MN/MX is low 8086 is configured tosupport multiprocessor system.The AD0-AD15 lines are a 16bit multiplexedaddressed or data bus. During the 1st clock cycleAD0-AD15 are the low order 16Bit adders. The8086 has a total of 20 address line ,the upper 4lines are multiplexed with the state signal thatis A16/S3 , A17/S4 , A18/S5 , A19 /S6.Duringthe first clock period of a best cycle the entire 20bitaddress is available on these line. During all otherclock cycles for memory and i/o operations AD15-AD0 contain the 16 bit dataandS3,S4,S5,S6 become the status line .S3 and S4are decoded as followsA17/S4 A16/S3 Function0 0 Extra Segment0 1 Stack Segment1 0 code or No segment1 1 Data SegmentThere for the 1st clock cycle of an instructionexecution the A17/S4 And A16/S3 pins Specifywhich Segment register generate the segmentportions of the 8086 address
  3. 3. BHE/S7 is used as best high enable during the1st click cycle of an instruction execution .the BHEcan be used in conjunction with AD0 to select thememoryRD is low when the data is read from memory orI/O location .TEST is an input pin and is only used by the waitinstruction .the 8086 enter a wait state afterexecution of the wait instruction until a low is Seanon the test pin.INTR is a maskable interrupt input.NIM is the non maskable interrupt input.RESET is the system set reset input signal itterminates all the activities itclear PSW,IP,DS,SS,ES and the instructionQueue.DT/R(Data Transmit or receive ):is an o/p signalrequired in system that uses the data bustransceiverALE is an address latch enable . Is an o/psignal provided by the 8086 and can be used todemultiplexed AD0 to AD15 in to A10 toA15 andD0 to D15.M/IO is an 8086 output signal to distinguish amemory access and i/o access.
  4. 4. WR is used by the 8086 for performing writememory or write i/o operation .INTA(interrupt acknowledgement signal )INTA is the interrupt acknowledgment signalHOLD and HOLDAa high on the HOLD pin indicates that anothermaster is required to take over the S/M busCLK clock provides the basic timing signals for the8086 and bus controls .-->