Detection of small delay defects using on chip circuits.

1. Transition fault detection using On-Chip
Architecture
Rahul Krishnamurthy(2011VLSI06)
ABV-Indian Institute of Information Technology and Management Gwalior,
Morena Link Road, Gwalior, Madhya Pradesh, INDIA - 474010.
March 21, 2013

2. Contents
Contents
1. Detection Approaches
Variation Aware Testing
K Longest Path Generation Algorithm
On-chip hardware for delay testing
At-Speed Testing
Faster than At-speed testing
Path delay characterization
2. Delay Measurement Mechanism
3. Vernier Delay Line based TDC
4. Modified Vernier Delay Line
5. OCDM

3. Detection Approach
Detection Approach
First approach1 is to model process variations and then use
the model with test generation mechanism.
In this approach process parameter combinations are
generated for each defect.
Test generation is continued until all the possible process
parameters are covered.
1
F. Hopsch et al, Variation-Aware Fault Modeling, in Asian Test Symp.,2010,pp.87-93.

4. Detection Approach
Example of first approach
Delay fault testing under process variation
The delays of the gates are described by Gaussian
distributions, and the red lines indicates actual delays.
To detect a delay fault on input line ‘a’, conventional delay
test generation would try to propagate a transition along the
longest path (a, c, e, g) in the circuit using the pattern
sequence ((an , bn ), (an+1 , bn+1 )) = ((0,1), (1,1)).
a
c
e
g
b
d
f

5. Detection Approach
Delay fault testing under process variation
Delay fault testing under process variation
If the actual delays in a circuit instance assume the values as
shown in Figure given below then the longest path is (a, f, g)
and the previous test is no longer valid.
Instead, the test sequence ((0,0), (1,0)) will detect the fault
a
c
e
g
b
d
f

6. Detection Approach
Second approach
Second Approach
Second approach covers a small delay defect by propagating
the defect through a number of different paths
Process variation is taken into consideration by searching K
longest paths instead of one.
It does not require explicit modelling of process variations and
can be assumed to be more computationally feasible than
variation aware testing.
Detection of a critical SDD in a manufactured circuit instance
is guaranteed as long as one of the K paths selected, is indeed
the longest sensitizable path.

7. Detection Approach
Third Approach
Third Approach
The third approach uses an on-chip circuit to perform delay
testing.
On-chip circuitry is used for:Faster than At-speed testing.
Path delay characterization.
Transition Fault Test
A transition fault test requires a pattern (V1,V2).
V 1 →Initialization pattern
V 2 →Launch pattern
Response of the CUT to the pattern V2 is captured at the
operational functional speed(AT-Speed).

8. Detection Approach
AT-Speed testing
At-Speed testing
Depending on the way transition is launched and captured,
two type of delay tests are defined.
Skewed load delay test(LOS)
The first vector V1 is scanned in (usually with a slow scan
clock) and is then replaced in the scan register by applying a
one-bit shift.

9. Detection Approach
Delay testing contd..
Broadside delay test(LOC)
V1 is scanned in and is then replaced by the output of
combinational logic in normal mode.
Figure : Example LOC
The At-Speed test is performed on the logic between scan
cells B and C.
An initial value of 0 is loaded into scan cell B. During the
same load, a 1 is loaded into scan cell A.

10. Detection Approach
Example of LOC
Example of LOC
The value at scan cell A results in a 1 at the functional D
input to scan cell B.
After the scan cells are loaded, the circuit is placed into
functional mode(scan enable = 0).
The first functional clock pulse will cause cell B to capture
the 1 at its D input.

11. Detection Approach
Example of LOC
Example of LOC
The 0-to-1 transition will propagate toward cell C.
A second clock pulse will capture the value at cell C.
Next, the captured values are unloaded and shifted out for
verification.
If a 1 was captured into cell C, the transition propagated
within the desired time between the launch and capture
clocks. The circuit is therefore functional.
If a 0 was captured, a timing defect exists.
The accuracy of the at-speed scan-pattern application is only
dependent on the accuracy of the launch and capture clocks.
Scan-chain loads can be performed at an entirely different
frequency.

12. Detection Approach
Design problems
Design Problem
In a ”launch-off-shift” pattern, the transition occurs in the
last shift in the load-scan chains.
The scan-enable must turn off very quickly. One clock is
pulsed in functional mode to capture the response at the end
of a path.
The LOS delay testing approach can provide better delay fault
coverage with smaller size of test pattern set as compared to
LOC approach.
LOS is usually avoided due to stringent time requirement for
scan enable clock.
In recent literature 2 3 work has been done to rectify this
problem.
2
3
Songwei Pei; Huawei Li; Xiaowei Li, ”An on-chip clock generation scheme for faster-than-at-speed delay testing,”
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2010 , vol., no., pp.1353,1356, 8-12
March 2010
Tayade, R.; Abraham, J.A., ”On-chip Programmable Capture for Accurate Path Delay Test and Characterization,”
Test Conference, 2008. ITC 2008. IEEE International , vol., no., pp.1,10, 28-30 Oct. 2008

13. Detection Approach
Faster Than At-speed testing
FTAS
Testing of transition faults using a clock faster than the rated
clock speed.
This test is effective in detecting delays smaller than the slack
period.
Problem → The increasing gap between maximum frequency
provided by the external ATE and operating frequency.
Factors like parasitic capacitance, resistance of probe and
tester skew affects speed of external ATE which makes
On-Chip clock generation circuits a better alternative.

14. Path delay characterization
Path delay characterization
Due to process variation the delay measurement is less
predictable using simulations.
Actual path delay is measured using on-chip circuits.
The output is then observed using external ATE.
Delay information is then used to detect outliers and for
silicon debug.

15. Delay Measurement Mechanism
Delay Measurement Mechanism
On-chip measurement architecture measures the time interval
between input and output of circuit and gives the output in
the digital form.
START
M:1
MUX
Path Delay Measurement
Circuit
M:1
MUX
ON CHIP PATH DELAY MEASUREMNT
STOP

16. Delay Measurement Mechanism
Basic Vernier Delay Line based TDC
Vernier Delay Line based TDC
A Vernier structure consists of a pair of tapped delay lines
with a flip-flop at each corresponding pair of taps.
td1
td1
td1
START
Q
D
D
Q
Q2
Q1
STOP
C
C
td2
Q
D
td2
Vernier Delay Line
Q3
C
td2

17. Delay Measurement Mechanism
Working of VDL
Working of VDL
A stop signal propagates through one of the delay chain, while
the start signal propagates through the other.
The time difference between the START and the STOP pulse
is decreased in each Vernier stage by tR = (td1 − td2 ).
The position in the delay line, at which the STOP signal
catches up with the START signal, gives information about
the measured time tX with tR resolution.
nX .tR ≤ tX ≤ (nX + 1).tR

18. Vernier Delay Line Simulation
Simulation setup
The VDL based TDC is simulated to detect a delay of 50ns.
td1 is 10ns delay buffer and td2 is 3.6ns delay buffer.
After every stage delay between the signal is reduced by 6.4ns.

19. Vernier Delay Line Simulation
Vernier Delay Line Simulation
Simulation Waveforms

20. Vernier Delay Line Simulation
Vernier Delay Line Simulation
Simulation Waveforms contd..

21. Vernier Delay Line Simulation
Vernier Delay Line Simulation
Simulation Waveforms contd..
According to nX .tR ≤ tX ≤ (nX + 1).tR
delay tX comes out be :7 × 6.4 ≤ tX ≤ 8 × 6.4

22. Vernier Delay Line Simulation
Conclusion of VDL Simulations
Conclusion of VDL Simulations
The VDL design is dependent on the type of transitions
generated on the critical path.
The VDL designed for a rising transition on clock signal will
not work for a falling transition on clock signal.
DATA
DATA
D
CLOCK
Q=0
D
Q=1
Q
clk
Positive edge
Trigered
DFF
Q
Positive edge
clk Trigered
DFF
CLOCK
Flip flop is not triggered by the clock

23. Modified Vernier Delay Line TDC
Modified Vernier Delay Line(MVDL) TDC
MVDL removes the dependency on transition by converting all
the transitions on the clock input to rising.
1
Q
D
Posedge D FF
1(If clock is a rising transition)
0(If clock is a falling transition)
CLK
Reset
Rising Transition
Figure : Transition detector

24. Modified Vernier Delay Line TDC
MVDL
MVDL contd..3
MODE
STOP
td1
Q
D
td1
td1
D
Q1
Q
Q
D
Q2
Q3
C
C
C
START
td2
td2
td2
Shiftclk
Modified Vernier Delay Line
3
Ramyanshu Datta, Antony Sebastine, Ashwin Raghunathan, Gary Carpenter, Kevin Nowka, and Jacob A. Abraham, Onmeasurement based response analysis for timing characterization, J. Electron. Test. 26 (2010), no. 6, 599-619.

25. Measurement in Picosecond range
Measurement in Picosecond range
Measurement in picosecond range using vernier delay line is
limited due to the setup time of Flip flops.
Time difference between clock and data signal less than setup
time is lost.
ts2
ts1
Q=1
DATA
Q=0
DATA
ts1 less than setup time
ts2 greater than setup time
D Flip Flop
CLOCK
D Flip Flop
CLOCK
Setup time violation

26. Measurement in Picosecond range
Picosecond range measurement using MVDL
Simulation Setup
Simulation measures the path delay between 6gat and 23gat
of c17 4 benchmark circuit using MVDL.
td1 is 134ps buffer and td2 is 52ps buffer.
Figure : C17 benchmark circuit
4
http://www.ece.uic.edu/ masud/iscas2spice.htm

27. Picosecond range measurement using MVDL
Simulation Waveforms
Gat6 is the start signal and Gat23 is the stop signal.
Q0=1 shows that the Gat6 arrives before Gat23.
Start and Stop Waveforms

28. Picosecond range measurement using MVDL
Picosecond range measurement using MVDL
Simulation Waveforms contd..
The difference between the start and stop signals is reduced
by the 82ps in the stage 1.
Q1=1 shows that the signal Gat23 lags behind Gat6 by more
than 82ps.
STAGE1 Waveforms

29. Picosecond range measurement using MVDL
Picosecond range measurement using MVDL
Simulation Waveforms contd..
The difference between the start and stop signals is again
reduced by 82ps in the stage 2.
Q2=0 shows that the difference between the two signals is
less than 164ps.
STAGE2 Waveforms

30. Picosecond range measurement using MVDL
Picosecond range measurement using MVDL
Simulation Waveforms contd..
The difference between the signals in stage3 is again reduced
by 82ps.
Q3=0 indicates that the difference between start and stop
signals is less than 246ps.
STAGE3 Waveforms

31. Picosecond range measurement using MVDL
Picosecond range measurement using MVDL
Simulations Conclusion
For a large delay difference, the number of delay stages
required is also large.
If we reduce delay stages by increasing the delay range, then
resolution is reduced.
The main drawback of VDL is the fixed delay range in each
stage.

32. On chip delay measurement circuit
On chip delay measurement circuit
In OCDM the delay ranges of each stage is not same.
The first stage has the largest delay range and then the delay
range of subsequent stages is reduced by half.
This helps in achieving detection of maximum range as well
smallest range with same circuit.

33. On chip delay measurement circuit
On chip delay measurement circuit(OCDM)
On chip delay measurement circuit(OCDM) contd..5
Figure : OCDM circuit
5
Songwei Pei, Huawei Li, and Xiaowei Li, A high-precision on-chip path delay measurement architecture, Very Large Scale I
(VLSI) Systems, IEEE Transactions on 20 (2012), no. 9, 1565-1577.

34. On chip delay measurement circuit
On chip delay measurement circuit(OCDM)
On chip delay measurement circuit(OCDM) contd..
Stage2
Stage1
Revert Back
Q=1
Start2
Q=0
400
Start1
t1+200
200
Start1
t1+400
t1
t1
Stop2
Stop1
t2
t2
Stop1
t2
t2
Stage3
Q=0
Start2
t1+200
t1+200
Stop2
t2
t1+250
50
Stop2
Stop2
t2
Q=0
Start2
Start2
t1+300
100
Stop2
Revert Back
Stage4
Revert Back
Start2
t2
t2
Stage6
Stage5
25
Start2
Start3
t1+200
Q=1
t2
12.5
t1+225
t2
Start3
Q=1
t1+237.5
Stop3
Stop3
Stop3
Stop2
Start3
t1+225
t2
Figure : OCDM circuit example
t2

35. On chip delay measurement circuit
On chip delay measurement circuit(OCDM)
On chip delay measurement circuit(OCDM) contd..
Y is the input signal of circuit. Passed through Upper Delay
Unit.
X is the output signal of the circuit. Passed through Lower
Delay Unit.
If the delay difference between Buf1 and Buf2 of the stage is
more than the difference between the X and Y, then output is
Q=0.
If the delay difference between Buf1 and Buf2 of the stage is
less than the difference between the X and Y, then output is
Q=1.

36. On chip delay measurement circuit
On chip delay measurement circuit(OCDM)
On chip delay measurement circuit(OCDM) contd..
When the Q is 0 then the output of buffer A is selected by the
multiplexer as the output signal of that stage.
When Q=1 X passes through BUF2n and Y is passed through
BUF1n and difference between them is reduced by the delay
range of the stage.
Y1
Y2
X2
X1
(a)
Passed through Buf1 and Buf2. Delay between signals reduced.
Y2
Y1
X1
X2
(b)
Passed through buffer_A .Delay between signals unchanged.

37. On chip delay measurement circuit
On chip delay measurement circuit(OCDM)
OCDM Simulation
The delay between Y and X is set to 200ps.
Delay range of first stage is 286ps.
The delay range is greater than the 200ps, hence the signal
from buffer A will pass to output.
First stage Waveform

38. On chip delay measurement circuit
On chip delay measurement circuit(OCDM)
OCDM Simulation
Delay range of second stage is 140ps.
The delay between the signals X and Y is still 200ps.
The delay range is less than the difference between the
signals. Hence the output Q = 1. The signal through buf1
and buf2 will passed through the Multiplexer.
Second stage Waveform

39. On chip delay measurement circuit
On chip delay measurement circuit(OCDM)
OCDM Simulation
Delay range of third stage is 80ps.
Now the difference between the signals is 60ps, which is
greater than delay range of the stage. So the output is Q=0.
Third stage Waveform

40. On chip delay measurement circuit
OCDM Simulation Conclusion
OCDM Simulation Conclusion
Output of flip flop must attain a stable value before the
inputs arrives at the multiplexer.
OCDM requires additional buffers like BUF B in each stage to
delay the inputs to multiplexer by sufficient time.
The Buf A of a stage should be larger than Both BUF B and
BUF 1 of that stage to get proper output.

41. References
References
Ramyanshu Datta, Antony Sebastine, Ashwin Raghunathan,
Gary Carpenter, Kevin Nowka, and Jacob A. Abraham,
On-chip delay measurement based response analysis for timing
characterization, J. Electron. Test. 26 (2010), no. 6, 599–619.
M. Maymandi-Nejad and M. Sachdev, A digitally
programmable delay element: design and analysis, Very Large
Scale Integration (VLSI) Systems, IEEE Transactions on 11
(2003), no. 5, 871 –878.
Songwei Pei, Huawei Li, and Xiaowei Li, A high-precision
on-chip path delay measurement architecture, Very Large
Scale Integration (VLSI) Systems, IEEE Transactions on 20
(2012), no. 9, 1565 –1577.
H. Yotsuyanagi, H. Makimoto, and M. Hashizume, A boundary
scan circuit with time-to-digital converter for delay testing,

42. References
Test Symposium (ATS), 2011 20th Asian, nov. 2011, pp. 539
–544.
Yubin Zhang, Haile Yu, and Qiang Xu, Coda: A concurrent
online delay measurement architecture for critical paths,
Design Automation Conference (ASP-DAC), 2012 17th Asia
and South Pacific, 30 2012-feb. 2 2012, pp. 169 –174.