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Scan chain operation
PO/SOD
SI
SE
CLK
PI
Scan Pattern operates in one of two modes,
1) Shift Mode.
2) Parallel Mode.
Mode(Active input) is controlled by Scan_En pin.
In Shift mode the input comes from the output of the previous scan
cells or scan input port.
In parallel mode the input to each scan element comes from the
combinational logic block.
STEPS:-
●
Initialize scan cells; SE = 1
●
Hold the scan clock off & Apply the stimulus to primary inputs; SE = 0
●
Measure PO; SE = 0.
●
Pulse the clock to capture new value in to scan cell; SE = 0.
●
Enable the scan operation to unload and measure the captured values ;
SE = 1.

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Scan chain operation modes: shift and parallel

  • 2. PO/SOD SI SE CLK PI Scan Pattern operates in one of two modes, 1) Shift Mode. 2) Parallel Mode. Mode(Active input) is controlled by Scan_En pin. In Shift mode the input comes from the output of the previous scan cells or scan input port. In parallel mode the input to each scan element comes from the combinational logic block.
  • 3. STEPS:- ● Initialize scan cells; SE = 1 ● Hold the scan clock off & Apply the stimulus to primary inputs; SE = 0 ● Measure PO; SE = 0. ● Pulse the clock to capture new value in to scan cell; SE = 0. ● Enable the scan operation to unload and measure the captured values ; SE = 1.

Editor's Notes

  1. STEPS:- Here is an example design under test (DUT). I have shown a single scan chain (in red colour) in the circuit, with Scan In and Scan Out ports. Assume that scan flip‐flops are controlled by the Scan Enable(SE) signal. The first thing we should do is to put the scan flip‐flops into scan mode. We do this by using the Scan Enable signal. In this case, forcing SE to 1 enables the scan mode. And we start scanning in the test vector we want to apply. We will disable scan mode by forcing Scan Enable to 0. & force primary input (PI) values and measure the primary output (PO) values: force_PI and measure_PO. In order to push the output values of combinational blocks 1,2, and 3 into scan flip‐flops, we have to toggle the system clock. (capture pulse), all D flip‐flops (scan flip‐flops) will capture the values at their D input. Now, we are ready to shift‐out the captured combinational logic responses. while doing that, we will also shift‐in the next test vector. & we have set Scan Enable signal back to 1 to enable shifting. <number>