6. ENTITY provides a name to the component contains the port definitions in the interface list can contain some generic definitions which can be used to override default values entity identifier is generic interface_list; port interface_list; declarations begin statements end [entity] [identifier];
7. Example And a c b 2 input And gate 1. entity and is port (a, b: in bit; c : out bit); end and; 2. ENTITY and IS PORT( a, b : IN std_logic; c: OUT std_logic ); END and;
8. Architecture encapsulates the behavior and timing information contains a number of concurrent statements there can be multiple architecture bodies for a given entity architecture identifier of entity_name is declarations begin statements end [architecture] [identifier];
9. Example And a c b 2 input And gate architecture and_arch of and is; begin; c<= a and b; end and_arch;
10.
11. represents wires and storage elementsA Xor B sum C D And Or E And Carry F And Circuit diagram of full adder
12. Data Types Data type Scalar Type Composite Type Access Type File Type Record Integer Float Array Physical Enumeration
15. Dataflow Concurrent/ Continuously or Combinational Logic To give a signal a concurrent assignment SignalName <= expression; Inputs Outputs Full adder Sum (s) A B Carry out (c) Carry( in)
16. Dataflow(cont.) A Xor B Sum (s) Carry in (c _in) D And Or E Carry out (c_out) And F And Circuit diagram of full adder
17. Dataflow(cont.) library ieee; use ieee.std_logic_1164.all; ENTITY fulladder IS PORT ( a, b, c_in : IN BIT; s, c_out : OUT BIT); END fulladder; architecture fulladder_arch of fulladder is begin s<=a xor b xor c; c_out<= (a and b) or (b and c ) or (c and a); end fulladder_arch;
18.
19. Behavioral (cont.) ENTITY mux IS PORT ( a, b, c, d : IN BIT; s0, s1 : IN BIT; x, : OUT BIT); END mux; ARCHITECTURE sequential OF mux IS Process (a, b, c, d, s0, s1 ) VARIABLE sel : INTEGER; BEGIN IF s0 = ‘0’ and s1 = ‘0’ THEN sel := 0; ELSIF s0 = ‘1’ and s1 = ‘0’ THEN sel := 1; ELSIF s0 = ‘0’ and s1 = ‘0’ THEN sel := 2; ELSE sel := 3; END IF; CASE sel IS WHEN 0 => x <= a; WHEN 1 => x <= b; WHEN 2 => x <= c; WHEN OTHERS => x <= d; END CASE; END PROCESS; END sequential;
20.
21. Structural (cont.) HALF ADDER (USED FOR FULL ADDER) library ieee; use ieee.std_logic_1164.all; entity HA is port(a,b:in std_logic;s,c:out std_logic); end HA; architecture dataflow of HA is begin s<= a xor b; c<= a and b; end dataflow; library ieee; use ieee.std_logic_1164.all; entity OR2 is port(i1,i2:in std_logic; o:out std_logic); end OR2; architecture dataflow of OR2 is begin o<= i1 or i2; end dataflow;
22. Structural (cont.) --STRURAL DESCRIPTION OF FULL ADDER library ieee; use ieee.std_logic_1164.all; entity FA is port(x, y, ci :in std_logic;sum,co:out std_logic); end FA; architecture struct of FA is component HA port(a, b: in std_logic;s, c:out std_logic);end component; component OR2 port(i1,i2:in std_logic;o:out std_logic);end component; signal s1,c1,c2:std_logic; begin HA1:HA port map(x ,y ,s1 ,c1); HA2:HA port map(s1,ci,sum ,c2); ORG:OR2 port map(c1,c2,co); end struct;
23. Advantages of VHDL Standard language Concurrent & sequential statement processing No standard methodology Man machine readable documentation Versatile design support
24. References [1] Douglas L. Perry, VHDL: “programming by example”, McGraw-Hill, New York, 2002, Fourth Edition. [2] Wai-Kai Chen,” The VLSI Handbook “, CRC Press, USA, Second Edition. [3] Dr. Cecil alford tsai chi huang, “Digital design vhdl laboratory notes”, 1996, version 1.01, [4] http://en.wikipedia.org/wiki/Very-large-scale_integration [5] 1076 IEEE Standard VHDL Language Reference Manual
