The document discusses upgrading FPGA designs to SystemVerilog. It covers SystemVerilog constructs like interfaces that can improve FPGA design methodology. Case studies show how interfaces reduced integration time by enforcing protocol compliance. Ecosystem support and training resources are also presented to help with the adoption of SystemVerilog for FPGA designs.
3. About the presenter
Srinivasan Venkataramanan, CTO, www.cvcblr.com
http://www.linkedin.com/in/svenka3
Over 13 years of experience in VLSI Design & Verification
Designed, verified and lead several multi-million ASICs in
image processing, networking and communication domain
Worked at Philips, Intel, Synopsys in various
capacities.
Co-authored leading books in the Verification domain.
Presented papers, tutorials in various conferences,
publications and avenues.
Conducted workshops and trainings on PSL, SVA, SV,
VMM, E, ABV, CDV and OOP for Verification
Holds M.Tech in VLSI Design from prestigious IIT, Delhi.
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4. What is SystemVerilog?
Superset of Verilog-2001
IEEE 1800-2005 standard
More information @ www.SystemVerilog.org
Several books available:
SystemVerilog Assertions Handbook – Ajeetha, Ben Cohen,
Srinivasan, www.systemverilog.us
A Pragmatic approach to VMM adoption – Ajeetha, Ben,
Srinivasan
SystemVerilog for Designers, Stuart Sutherland
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5. SystemVerilog - Evolution
Classes,
Temporal Sequential
inheritance,
Property Regular
Definitions Expressions OOP based
polymorphism Testbench
Properties – capture temporal Constraint driven Constrained
randomization
Behavior: Assertion, Functional Coverage
Semaphores Random Data
Assumption, Coverage Inheritance
Mailboxes Generation
SVA Polymorphism
Queues,
Covergroup,
Virtual Interface
MDAs Data structures Associative
sampling
enums & Dynamic
arrays
Strings Enhanced programming Verilog 2001
(do while, break, continue,
++, --, +=. Etc.)
DPI – Quickly connect C/C++
Enhanced Design
Coverage &
Very efficient and ease of use Assertion API
Better logical blocks – Constructs, modeling
always_comb, _ff, _latch SV-Design
DPI interface
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6. SystemVerilog - User view
Has 5 major parts:
SVD – SystemVerilog for Design
SVA – SystemVerilog Assertions
SVTB – SystemVerilog Testbench
SV-DPI – Direct Programming Interface
for better C/C++ interface
SV-API – Application Procedural Interface
for Coverage, Assertion etc.
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7. Reference Books
Source A Pragmatic Approach to VMM Adoption 2006
for Tutorial ISBN 0-9705394-9-5, http://www.systemverilog.us
and Code
(7)
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8. SV Design-Data Types
Enhanced data types:
2-state (bit), logic
Potential memory & run time
improvement (2-state)
High level models can avail 2-state
Clearer descriptions: a Verilog reg is
NOT necessarily a “register”
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9. SV Design – Data types
User Defined types
Enums – local, typedef
Strict type checking, typecast
Better modeling style, easy to read,
maintain
State encoding - via language (not via
tool scripts)
Ease of debug, waveform
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10. SV Design – logic modeling
Verilog RTL – only always block
Combinatorial & Sequential
Inference by sensitivity list
One of the top 10 error prone usages – more for
newbie
SV: Enhanced Modeling
always_comb
always_ff
always_latch
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11. What logic is being modeled?
Modeling
combinatorial logic?
Use always_comb
Modeling Sequential
logic?
Use always_ff
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12. What logic is being modeled?
Modeling Latch?
Use always_latch
Reduces Synthesis-
Simulation discrepancies
Language captures design
intent (not pragmas, tool
settings)
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13. Abstract modeling - struct
C-like struct
Well proven
data structure
abstraction
technique
Cut down
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17. Old fashioned hook-up–
Verilog description
Too verbose
Highly error
prone
Maintenance
head-ache
Not easy to
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reuse
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18. Typical sub-systemusing Verilog
Modeled
AHB AHB
Master1 Master2
AHB AHB
Slave1 Slave2
SoC is built using IPs – lot of ReUse
Individual blocks pre-verified in standalone
Most Bugs Occur Between Blocks
A good number of “Wiring” Errors
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20. Interface
interface simple_bus; // Define the interface module cpuMod(simple_bus b, input bit
logic req, gnt; clk);
...
logic [7:0] addr, data;
endmodule
logic [1:0] mode;
logic start, rdy;
endinterface: simple_bus module top;
logic clk = 0;
simple_bus sb_intf; // Instantiate the
module memMod(simple_bus a, // Use the interface
simple_bus interface memMod mem(sb_intf, clk);
input bit clk); cpuMod cpu(.b(sb_intf), .clk(clk));
logic avail; endmodule
// a.req is the req signal in the ’simple_bus’
interface
always @(posedge clk) a.gnt <= a.req &
avail;
endmodule CVC Copyright 2008
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21. Assertion-Based Verification
It’s a verification technique
Instruments requirements with assertions
Clarifies requirements with executable language
Enables tools to preview assertion waveforms
Instruments design with assertions
Added visibility
White-box testing into its internal state
Provision for functional coverage information
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22. Applying ABV - Bus based SoC
Simulate
What happened during sim?
Any protocol violation?
How many RW?
Was xfer interrupted?
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23. Use assertions sparingly
Non-intrusive
Works with any existing flow
The more you add, the more you gain
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24. Ross Video – SV verification
for FPGAs
The Ross Video team created a robust verification
environment utilizing the VMM's built-in:
self-checking
scenario generation
transaction-level channels
transactors and
messaging services.
Extensive use of SystemVerilog assertions (SVA)
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25. Advantages of interface
customer success stories
Better design style
Disambiguate the communication
Forces to have a clear interface
specification upfront – takes little more
time, but saves much more later on
Reduces integration time
Add Assertions to interface, every block
using it shall have to comply with the
protocol
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30. SV & FPGA advanced
technologies
With adoption of SV, modern design
paradigms emerge
ASIC prototyping – EVE Design systems
Jasper’s ActiveDesign is one such
technology
Can create waveforms for AHB, AXI etc.
right from RTL
No TB required, plain RTL + ActiveDesign
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31. Jasper’s ActiveDesign
Capture “information” during RTL design
phase:
Designer makes an assumption about the
latency of output, FIFO size etc.
“show me a proof/witness/waveform” for such
an occurrence
Can we optimize the latency to say 5
What-if I change the FIFO size to 32 here etc.
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