Optimizing ARM cortex a and cortex-m based heterogeneous multiprocessor systems for rich embedded applications - k.dave
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The document discusses optimizing heterogeneous multiprocessor systems using ARM Cortex processors. It covers topics like system design considerations, software challenges, and ARM's activities to make heterogeneous computing easier. Specifically, it addresses issues like memory mapping, interrupt handling, communication between processors, and security models when combining Cortex-A, Cortex-R, and Cortex-M processors on a single system.
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Optimizing ARM cortex a and cortex-m based heterogeneous multiprocessor systems for rich embedded applications - k.dave
- 1. ©ARM 2017 Optimizing ARM Cortex-A and Cortex-M based heterogeneous multiprocessor systems for rich embedded applications Kinjal Dave Embedded World, Nuremberg, 2017 Senior product manager, CPU Group 16th March 2017
- 3. ©ARM 20173 Topics System design Software Introduction § Why heterogeneous processing? § Use cases § Terminology
- 4. ©ARM 20164 Thanks for reading For more information on ARM Cortex-A and Cortex-M processors visit arm.com Sign-up for the latest news and information from ARM
- 5. ©ARM 20175 Modern compute systems have diverse workloads Power Time Sleep mode Interactive mode Ambient mode
- 6. ©ARM 20176 Diversity of workloads across markets
- 7. ©ARM 20177 Why heterogeneous computing? “Right-sized processing” Increase system performance Increase system efficiency Reduce system cost
- 8. ©ARM 20178 ARM architecture for diverse computing needs Cortex-A Highest performance Optimized for rich operating systems Cortex-R Fast response Optimized for high performance, hard real-time applications Cortex-M Smallest/ lowest power Optimized for discrete processing and microcontrollers
- 9. ©ARM 20179 Heterogeneous systems are extremely diverse MCU CPU GPU ISP Video Display Audio DSP DDR Interconnect A heterogeneous system using different compute elements A heterogeneous subsystem using ARM Cortex processors
- 10. ©ARM 201710 Heterogeneous multicore processors Multicore HeterogeneousHomogeneous Performance asymmetry Functional asymmetry § Same ISA § Same microarchitecture § Same view of memory § Same ISA § Different microarchitecture § Same view of memory § OS/ Software symmetry § Different ISA § Different microarchitecture § Different view of memory § OS/ Software asymmetry Interconnect Interconnect Cortex-A + Cortex-M systems Interconnect
- 11. ©ARM 201711 Use cases of HMP systems Cortex-A Rich OS, high performance Cortex-R Modem Real-time control Cortex-M System control, sensor fusion Sensor fusion System control Mobile ADASWearables
- 12. ©ARM 201712 Use cases of HMP systems in embedded Cortex-A Rich UI and OS, high performance Cortex-M Real-time control and monitoring Deterministic sensor control Real-time monitoring MedicalConsumerIndustrial
- 13. ©ARM 201713 System design Topics Introduction Software ARM activities § System design considerations § Security models
- 14. ©ARM 201714 Architectural differences between Cortex families Cortex-A Cortex-R Cortex-M Lower power, smaller area Higher performance Rich OS/ RTOS RTOS only 32/64-bit ARM &Thumb ISA 32-bit ARM &Thumb ISA Thumb ISA SW-managed interrupts HW-managed interrupt AMBA AXI AMBA AHB/AXIAMBA AXI Deterministic SW-managed Operating system Instruction set Interrupts Bus interface
- 15. ©ARM 201715 System design considerations § How to address the memory map differences? § How to distribute interrupts? § How to handle inter-processor communication? § How to handle Secure/Non-secure state communication? Generic HMP compute subsystem using Cortex processors Interconnect Shared L2 AHB interconnect Local memory DMC DDR Cortex-A subsystem Cortex-R subsystem Cortex-M subsystem AHB interconnect TimerSensor SRAM
- 16. ©ARM 201716 Architectural support for ARM TrustZone ARMv6-M, ARMv7-M ARMv8-AARMv7-A ARMv8-M Trusted software Crypto TRNG Non-trusted (normal) Trusted (Secure) Trusted hardware Secure system Secure storage TrustZone § Isolate trusted resources from non-trusted § Isolate non-trusted software § Reduce attack surface of key components
- 17. ©ARM 201717 TrustZone for ARMv8-A and ARMv8-M TrustZone for ARMv8-A TrustZone for ARMv8-M Secure statesNon-secure states Secure statesNon-secure states Secure transitions handled by the processor to maintain real-time latency Secure app/libs OS support API / Secure OS Non-secure OS Non-secure app Secure app/libs Secure OS Rich OS, e.g. Linux Secure monitor
- 18. ©ARM 201718 TrustZone security using Cortex-M processors ARMv6-M and ARMv7-M processors § Always Secure or always Non-secure § Use case dependent Designer needs to be careful § Power management – Secure access only § Debug system needs to match security domain for each processor Shared L2 Cortex-A subsystem AHB interconnect Local memory System Control Processor (SCP) Power control Always Secure (secure boot) Interconnect DMC DDR AHB interconnect Local memory Audio subsystem Audio interface Always Non-secure Cortex-M subsystem
- 19. ©ARM 201719 TrustZone for ARMv8-M: More flexibility for designers Non-secure Non-secure Secure Secure Cortex-A processor Cortex-M processor (ARMv8-M) Shared secure world (e.g. Cortex-M as a smart DMA engine) Shared L2 Cortex-A subsystem AHB interconnect Local memory Interconnect DMC DDR AHB interconnect Local memory Audio subsystem Audio interface Cortex-M subsystem Secure/ Non-secure Smart DMA engine
- 20. ©ARM 201720 Software Topics Introduction System design § Overview of software challenges § Making software development easier
- 21. ©ARM 201721 Overview of software challenges Developer productivity Usability, portability, debugging Data sharing Is coherency necessary? Task partitioning How to optimally partition tasks?
- 22. ©ARM 201722 Standardization of software interfaces § CMSIS adopting OpenAMP § Cortex Microcontroller Software Interface Standard (CMSIS) § Now open source on Github § OS support for HMP systems § Remote Processor Messaging (RPMsg) for inter-processor communication § Management framework using remoteproc Cortex-A processor Memory subsystem Cortex-M processor SRAM Rich OS/ RTOS RTOSRPMsg remoteproc
- 23. ©ARM 201723 Debug Linux and RTOS apps from a single tool Cortex-A Cortex-M RTOS systemLinux kernel Linux application JTAG TCP/IP CoreSight Microcontroller application Debug: ü The Cortex-M application ü The Cortex-A Linux kernel ü The Cortex-A Linux application DS-MDK debugger enables complete visibility to all software applications in the heterogeneous system
- 24. ©ARM 201724 § Quickly discover hot spots of your application § Simplifies efficient task partitioning on your system § System-wide views as bottlenecks are often outside the CPU Performance tuning for HMP systems
- 25. ©ARM 201725 Summary You can build heterogeneous multicore systems today using different Cortex processors and other system IP ARM architecture enhancements make future HMP systems better System and software considerations required in the context of use cases ARM is working on several activities to make HMP easier
- 26. The trademarks featured in this presentation are registered and/or unregistered trademarks of ARM Limited (or its subsidiaries) in the EU and/or elsewhere. All rights reserved. All other marks featured may be trademarks of their respective owners. Copyright © 2017 ARM Limited ©ARM 2017