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Mullbery& veriest track g


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Mullbery& veriest track g

  1. 1. © 2010 Mulberry1 Ltd, Veriest-Venture Ltd
  2. 2. Mulberry 1 Your One Solution house <ul><li>Mulberry 1 Est. in 2006 </li></ul><ul><li>Provides First-Class multi-disciplinary outsource Solutions & Design Services. </li></ul>Alliances: Mulberry?
  3. 3. What is a TALL TALE? <ul><li>TALL TALE is a kind of folk tale </li></ul><ul><li>Focuses typically popular beliefs , Internet rumors, or other myths. </li></ul><ul><li>A tall tale is based on a real fact, heroes of tall tales are 'larger than life'. </li></ul><ul><li>Tall tale heroes solve problems in funny ways that are hard to believe. </li></ul>ARE you a FPGA TALL-TALE Hero?
  4. 4. Are You Influenced / Exposed to Tall Tales? <ul><li>FPGA is a good candidate implementing market needs for fast response, complex and involving solutions </li></ul><ul><li>Need fast infrastructure ramp up? </li></ul><ul><li>Have limited Budget ? </li></ul><ul><li>Have tight schedule? </li></ul><ul><li>Need to provide tested product and fast? </li></ul>TOO MUCH TO DO and have LACK of RESOURCES?
  5. 5. Are You Influenced / Exposed to Tall Tales? <ul><li>Now you are guided by </li></ul><ul><li>Tall Tales. </li></ul><ul><li>You wish to believe they are true </li></ul>YES
  6. 6. Planning – Tall Tales <ul><li>FPGA does not require specific planning. “Everything is programmable, Keep 50% utilization and everything will be OK ” </li></ul><ul><li>Real fact – may be true for simple implementations </li></ul>
  7. 7. Planning – Expert’s opinion <ul><li>FPGA technology and capacity today (Millions of gates, 100s of MHz) is comparable to ASIC implementation complexity. </li></ul><ul><li>FPGA is usually located in the system’s core and affected by many factors and professionals in the team – ASIC architecture, system design, SW, HW. </li></ul><ul><li>FPGA might be at the whole project bottle neck. </li></ul><ul><li>Strategic decisions are very important – Pinout, vendor, device type, capacity, speed, etc. </li></ul>
  8. 8. Design – Tall Tales <ul><li>FPGA design is like ASIC design , any ASIC Designer can do it. just write your code as you wish and the tools will optimize and do the rest. </li></ul><ul><li>“ Board designer is free to choose the pinout and FPGA tools will align later to the requirements” </li></ul><ul><li>or </li></ul><ul><li>“ Let the tools decide - Vendor knows the best pinout fit” </li></ul><ul><li>Real fact – Functional RTL design is similar, Tools decision is a good start. </li></ul>
  9. 9. Design – Expert’s opinion <ul><li>RTL design should be FPGA FRIENDLY , especially @ high speed. (Bad Example:66 logic levels ) </li></ul><ul><li>FPGA design requires high BE skills and not only logic design – Physical flow, timing closure, synthesis process, tools, etc. </li></ul><ul><li>Resources are still limited in comparison to ASIC. </li></ul><ul><li>Deep understanding of the FPGA internal architecture is crucial while trying to optimize the design. Initial pre-placement will result better performance. </li></ul>
  10. 10. Verification – Tall Tale <ul><li>“ WE DO NOT NEED TO GET THOSE VERIFICATION ENGINEERS INVOLVED.” </li></ul><ul><li>“ FPGA has fast turn around, test it in the lab, no need for verification efforts” </li></ul><ul><li>“ FPGA verification, same as ASIC verification would consume huge resources – thus we should avoid it” </li></ul><ul><li>Real fact –ASIC Verification is Complex task, FPGA configuration is fast </li></ul>
  11. 11. Verification – Expert’s opinion <ul><li>Debug time in the LAB is very costly, debug cycle involves many tools and equipments – test stations are limited. </li></ul><ul><li>FPGA verification strategy fits into the project scope: </li></ul><ul><ul><li>Simplified environment and fast rampup. </li></ul></ul><ul><ul><li>Coverage and test plans are aligned with targets. </li></ul></ul><ul><ul><li>Specific scenarios reproduction capabilities. </li></ul></ul><ul><li>Good test plan partitioning – what should be tested by verification team and what will be covered in the LAB. </li></ul>
  12. 12. Summery <ul><li>Plan- Involve FPGA process as early as possible </li></ul><ul><li>Design – FPGA is an expertise of itself. </li></ul><ul><li>Verify – Use FPGA verification strategy </li></ul><ul><li>FPGA Flow TALL TALES are nice. </li></ul><ul><li>EXPERTS & TOOLS are a MUST! </li></ul>
  13. 13. <ul><li>Thank You! </li></ul>[email_address] 054 - 428-4574 [email_address] 054 - 592-7962