C:\fakepath\micrologic track c


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C:\fakepath\micrologic track c

  1. 1. nanoRVInteractive™ Nanometer Reliability
  2. 2. Nanometer Reliability – Current Verification Flow <ul><li>Done only when large IC layout blocks are ready ‏ </li></ul><ul><li>Long RV time </li></ul><ul><li>Reliability Corrections lead to DRC, LVS Re-Verification </li></ul><ul><li>Reliability issues waived due to Tape Out schedules </li></ul>
  3. 3. Nanometer Era – Challenges <ul><li>Process Shrink – integrating more transistors on a die ‏ </li></ul><ul><li>IC’s complexity increase – Thousands of Design Rules </li></ul><ul><li>Performance increase with lower current consumption </li></ul><ul><li>New materials, new physical phenomenon </li></ul><ul><li>Design constraints </li></ul><ul><li>Package complexity </li></ul>
  4. 4. Reliability Challenges <ul><li>Hot Electron Effect & Oxide Degradation </li></ul><ul><li>Electromigration & Self Heat </li></ul><ul><li>Oxide Breakdown </li></ul><ul><li>Latchup </li></ul><ul><li>ESD – Electrostatic Discharge </li></ul><ul><li>Voltage Drop </li></ul><ul><li>Soft Errors </li></ul>
  5. 5. Hot Electron Effect & Oxide Degradation <ul><li>Electrons/Holes that gained high kinetic energy due to a strong electric field </li></ul><ul><li>Especially in MOS devices </li></ul><ul><li>Electrons/Holes can get injected and trapped in wrong areas </li></ul><ul><li>The term “Hot” means the range of kinetic energy to escape from the atom’s path </li></ul>
  6. 6. Electromigration & Self Heat <ul><li>Hot Electron Effect & Oxide Degradation </li></ul><ul><li>Electron movement induced by the current in the metal power lines causes metal ions to migrate </li></ul><ul><li>POWER Electromigration – Uni Direction EM </li></ul><ul><li>Switching signals are defined as Bi-Direction EM </li></ul><ul><li>EM is accelerated by high temperature </li></ul>
  7. 7. Electromigration & Self Heat (Cont.) Short Circuit OPEN Circuit Images Source: Computer Simulation Laboratory ; Clark University
  8. 8. Oxide Breakdown <ul><li>Hot Electron Effect & Oxide Degradation </li></ul><ul><li>The destruction of an oxide layer in a semiconductor device </li></ul><ul><li>Oxide layers are used in many parts of devices </li></ul><ul><ul><li>Gate oxide between the metal and the semiconductor in MOS transistors </li></ul></ul><ul><ul><li>Dielectric layer in capacitors </li></ul></ul><ul><ul><li>Inter-layer dielectric to isolate conductors </li></ul></ul><ul><li>Oxide breakdown is also referred to as 'oxide rupture' or 'oxide puncthrough' </li></ul>
  9. 9. Latchup <ul><li>Hot Electron Effect & Oxide Degradation </li></ul><ul><li>Short circuit which can occur in an improperly designed circuit </li></ul><ul><li>Unintended creation of a low impedance path between the power supply </li></ul><ul><li>Triggering a parasitic structure which disrupts proper functioning of the part and possibly even leading to its destruction due to over current </li></ul>
  10. 10. ESD – Electrostatic Charge <ul><li>Sudden and momentary electric current that flows between two objects at different electrical potentials caused by direct contact or induced by an electrostatic field </li></ul><ul><li>An IC connected to external ports is susceptible to damaging ESD pulses from the operating environment and peripherals </li></ul>
  11. 11. Voltage Drop <ul><li>T he reduction in voltage in an electrical circuit between the source and load due to wire res. & current drawn from power </li></ul><ul><li>Causes lower voltage than required, which leads to larger TPDs, also effect Noise </li></ul>
  12. 12. Soft Errors – Datum Error <ul><li>Transient faults that occur in VLSI circuits due to external radiation and affect the logic states of sensitive nodes </li></ul><ul><li>Generally occur from nuclear decay of packaging materials or atmospheric particles accelerated towards the earth by cosmic rays </li></ul><ul><li>Neutron radiation interferes with charges held in sensitive nodes in circuits causing soft errors - or SEU (Single event upset) </li></ul><ul><li>Generally affect storage elements such as memory, latches and registers </li></ul>
  13. 13. Current verification <ul><li>EDA offers standard verification tools (Cadence, Synopsys, Apache) </li></ul><ul><li>IC Design houses develop in-house flows </li></ul><ul><li>Synthesis tools include built-in reliability considerations (P&R) </li></ul>
  14. 14. Current Solutions <ul><li>Circuit Designs – Current Limiters (Frontend) </li></ul><ul><li>Signals & Power metals width (Backend) </li></ul><ul><li>Manufacturing improvements (Fabrication) </li></ul>
  15. 15. Future Innovation <ul><li>Early Reliability Analysis During IC Layout Design </li></ul><ul><ul><li>Find problems as they are created </li></ul></ul><ul><ul><li>Fix them when it is easy </li></ul></ul><ul><ul><li>Reach signoff checks with significantly fewer issues </li></ul></ul><ul><li>Analysis Correlation with simulation results </li></ul><ul><li>Critical signals timely analysis (Clocks, Critical Paths, Etc) </li></ul><ul><li>Look Ahead analysis during construction, creating Signoff Ready design </li></ul>
  16. 16. Early Detection – Example #1
  17. 17. Early Detection – Example #2
  18. 18. Early Detection – Example #3
  19. 19. Thank you for your time!
  20. 20. Thank you for your time!