Three dimensional integration of cmos inverter

1. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 –
6464(Print), ISSN 0976 – 6472(Online), Volume 5, Issue 11, November (2014), pp. 01-05 © IAEME
1
THREE DIMENSIONAL INTEGRATION OF CMOS
INVERTER
Dattaprasad Madur1
, Dr. Deepak Bhoir2
, Asst. Prof. Swapnali Makdey3
Department of Electronics, Fr. Conceicao Rodrigues College of Engineering
Fr. Agnel Ashram, Bandstand, Bandra (W), Mumbai: 400 050, India
ABSTRACT
The Performance of a memory device plays a vital role in a computing system. The Processor
architecture decides the performance of system. Also the memory device has contribution to the
system’s performance. Some aspects related to memory viz. hit, miss, latency, etc. are the key terms
which has impact to the system’s performance. Now a day, the advanced processor architecture
revolution has become crucial and is ceasing in the improvement of faster fetching, decoding and
execution. The New concept of three dimensionally integrated memories tends to give a better
performance than the two dimensionally integrated memory. The Approach of 3DI is to stack the
multiple dies of a memory which gives shorter interconnections; low resistance and low power
consumption, faster passage of control signals and reduction of a die area as compared to the
previous integration technology at the cause of increasing the cost and system complexity. Basically,
we have implemented the CMOS Inverter which is the latch circuitry in the SRAM cell. We have
simulated a 3D integrated CMOS Inverter in 40nm process technology.
Keywords: 3DI, CMOS, Memory etc.
I. INTRODUCTION
Three dimensional integration of a circuit or a complete system brings a new approach in the
VLSI stream. The SiP type of 3DI is simple, inexpensive and straight forward. The Other type i.e.
Through Silicon Vias (TSV) based 3D integration give more benefits. Some of them are short
connection, reduced RC delays, small area etc[2]. 3DI using the TSV is a promising approach to
coping with the challenges faced by the current 2D technology. A TSV-based 3D IC is implemented
by stacking multiple dies which are vertically connected by TSVs. This may shorten the global
interconnects of a 3D IC and greatly improve its performance and power consumption. High
bandwidth is achieved by the increase of IO channels provided by the TSVs, which also reduces the
unnecessary waste of energy during data movement.
INTERNATIONAL JOURNAL OF ELECTRONICS AND
COMMUNICATION ENGINEERING & TECHNOLOGY (IJECET)
ISSN 0976 – 6464(Print)
ISSN 0976 – 6472(Online)
Volume 5, Issue 11, November (2014), pp. 01-05
© IAEME: http://www.iaeme.com/IJECET.asp
Journal Impact Factor (2014): 7.2836 (Calculated by GISI)
www.jifactor.com
IJECET
© I A E M E

2. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976
6464(Print), ISSN 0976 – 6472(Online), Volume 5, Issue 1
A 3D circuit is the stacking of regular 2D circuits. The Advances on the fabricatio
packaging technologies allowed interconnecting stacked 2D circuits by using 3D vias. 3DI
technology could help to provide tremendous amount of IO bandwidth to the processor with very low
energy, using thousands of TSVs between processor and the memor
deliver Tera-scale performance, which will demand 100’s of GB/s of memory bandwidth where as a
traditional memory subsystem solution will not be sufficient
II. DESIGN AND IMPLEMENTATION OF 40nm CMOS INVERTER
2.1 Creating the 3D model
As we know the 3D model is the
model on the planar surface. Following Figs. explain you this.
Fig.1: Layer thicknesses and z
in the CMOS process
Fig.1. explains you the parameters to be defined in the process file for 3D model i.e.
thicknesses of STI, ILD and M1 and also the z
respectively whereas Fig.2. Explain
International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976
6472(Online), Volume 5, Issue 11, November (2014), pp. 01
2
A 3D circuit is the stacking of regular 2D circuits. The Advances on the fabricatio
ed interconnecting stacked 2D circuits by using 3D vias. 3DI
technology could help to provide tremendous amount of IO bandwidth to the processor with very low
energy, using thousands of TSVs between processor and the memory. A 3D integrated memory could
scale performance, which will demand 100’s of GB/s of memory bandwidth where as a
traditional memory subsystem solution will not be sufficient [2].
DESIGN AND IMPLEMENTATION OF 40nm CMOS INVERTER
the 3D model is the introduction of third axis i.e. z-axis in the respective layout
. Following Figs. explain you this.
Layer thicknesses and z-coordinates Fig.2: 40nm CMOS Inverter Layout
CMOS process
Fig.3: 3D Inverter
the parameters to be defined in the process file for 3D model i.e.
thicknesses of STI, ILD and M1 and also the z-coordinates of specific layers (z0, zSTI, Zbottom etc.)
Explain the layout design of Inverter.
International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 –
1-05 © IAEME
A 3D circuit is the stacking of regular 2D circuits. The Advances on the fabrication and
ed interconnecting stacked 2D circuits by using 3D vias. 3DI
technology could help to provide tremendous amount of IO bandwidth to the processor with very low
y. A 3D integrated memory could
scale performance, which will demand 100’s of GB/s of memory bandwidth where as a
axis in the respective layout
40nm CMOS Inverter Layout
the parameters to be defined in the process file for 3D model i.e.
(z0, zSTI, Zbottom etc.)

3. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976
6464(Print), ISSN 0976 – 6472(Online), Volume 5, Issue 1
class CMOS004Params()
[ ('lmd', 0.02),
('Tsub',2),
('TBOX',0.03),
(‘TSTI’,0.01),
('Tox',3e-3'),
('Tpoly',0.20),
('TTiSi2',0.02),
('TM0',0.2),
('TILD',1),
# sub doping
('Nsub', 2e17')
# S/D extention doping
('Nsde_n', 2.06338e2'),
('Nsde_p', 2.87375e19')]
(a) Definition of all process parameters
Table 1 (a) and (b) give
process of making a 3D structure respectively.
Fig.4: Different views of 3D Inverter (+Z, +X and +Y)
2.2 40nm 3D CMOS Inverter
First of all, the optimized layout of inverter has to be drawn. Secondly, write down the
process file of particular technology say 40nm. Combine these two, resulting into the 3D model.
Fig.3. shows the generated 3D model of 40nm CMOS Inverter. Fig.4. shows the different views of
CMOS Inverter Model.
International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976
6472(Online), Volume 5, Issue 11, November (2014), pp. 01
3
Table 1
class CMOS004Params()
('Nsde_p', 2.87375e19')]
self.z0 = 0.0
self.zbottom = self.z0 - Tsub
self.zBOX = self.z0 - TSTI -
self.zSTI = self.z0 - TSTI
self.zpoly = self.z0 + Tpoly
self.zTiSi2n = self.z0 + TTiSi2
self.zTiSi2p = self.zGe + TTiSi2
self.zpolyTiSi2 = self.zpoly + TTiSi2
self.zM0t = self.zpoly + TTiSi2 +TM0
self.zM1b = self.z0 + TILD
self.zM1t = self.zM1b + TM1
self.zM2b = self.zM1t + TIMD2
self.zM2t = self.zM2b + TM2
self.zmax = self.zM2b + TPass
self.Tpad = 0.1*TILD
rocess parameters (b) Pseudo Code for 3D structure
the details about the definition of the process parameters and the
of making a 3D structure respectively.
Different views of 3D Inverter (+Z, +X and +Y)
First of all, the optimized layout of inverter has to be drawn. Secondly, write down the
technology say 40nm. Combine these two, resulting into the 3D model.
shows the generated 3D model of 40nm CMOS Inverter. Fig.4. shows the different views of
International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 –
1-05 © IAEME
TBOX
TTiSi2
self.zTiSi2p = self.zGe + TTiSi2
self.zpolyTiSi2 = self.zpoly + TTiSi2
self.zM0t = self.zpoly + TTiSi2 +TM0
self.zM1t = self.zM1b + TM1
self.zM2b = self.zM1t + TIMD2
self.zM2t = self.zM2b + TM2
ss
(b) Pseudo Code for 3D structure
details about the definition of the process parameters and the
Different views of 3D Inverter (+Z, +X and +Y)
First of all, the optimized layout of inverter has to be drawn. Secondly, write down the
technology say 40nm. Combine these two, resulting into the 3D model.
shows the generated 3D model of 40nm CMOS Inverter. Fig.4. shows the different views of

4. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 –
6464(Print), ISSN 0976 – 6472(Online), Volume 5, Issue 11, November (2014), pp. 01-05 © IAEME
4
2.3 Circuit Simulation
The Resulting 3D Model is converted into the IC form for further simulation as shown in
fig.5. It shows pulse input without delay and the capacitive load at the output with supply voltage of
0.1 volts.
Fig.5: Circuit Schematic of CMOS Inverter
III. SIMULATION RESULTS
Following Figs. Show the transient characteristics and Steady state characteristics for the
capacitive load
Fig.6: Transient Characteristics Fig.7: Steady state Characteristics
Fig.8: Transient Characteristics with delay Fig.9: Static Power Curve

5. International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 –
6464(Print), ISSN 0976 – 6472(Online), Volume 5, Issue 11, November (2014), pp. 01-05 © IAEME
5
Summary of results of CMOS Inverter
Parameters Values
Lambda 20nm
Gate length 40nm
Supply Voltage 0.1 volts
Threshold Voltage 0.035 volts
Chip Area 0.342umଶ
Delay in the circuit 0.21nsec
Static power 9nWatts
Dynamic power 0.25f Watts~0.5nWatts
IV. CONCLUSION
Thus, this new concept of 3DI brings a new turn in the vlsi systems optimizing the above
parameters as compared to previous integrations from 2D to 2.9D.
ACKNOWLEDGEMENT
The Authors would like to thank Dr. Surendra Rathode from SPIT for the lab provision for
the Genius simulator, Mr. Amit Saini from Cadre Design Systems for his valuable support to this
work and Mr. Ajay Koli, Fr CRCE for his technical support.
REFERENCES
[1] Koyanagi et al, “Future System-on-Silicon LSI Chips”, IEEE Micro, July/August 1998.
[2] S. Borkar, et al, “3D Integration for Energy Efficient System Design”, DAC June 2011.
[3] Yangdong Deng and W.P. Maly. 2.5-dimensional vlsi system integration. Very Large Scale
Integration (VLSI) Systems, IEEE Transactions on, 13(6):668–677, June 2005.
[4] S. Tarzia, “A Survey of 3D Circuit Integration”, March 14, 2008.
[5] G. T. Goele et al., “Vertical Single Gate CMOS Inverters on Laser-Processed Multilayer
Substrates,” Proceedings of the IEEE International Electron Device Meetings, Vol. 27,
pp. 554-556, December 1981.
[6] P. Vasilis, “Interconnect-Based Design Methodologies for Three-Dimensional Integrated
Circuits,” PhD report at University of Rochester, New York, 2008.
[7] Rajinder Tiwari and R K Singh, “An Optimized High Speed Dual Mode CMOS Differential
Amplifier for Analog VLSI applications”, International Journal of Electrical Engineering &
Technology (IJEET), Volume 3, Issue 1, 2012, pp. 180 - 187, ISSN Print: 0976-6545,
ISSN Online: 0976-6553.
[8] P.Sreenivasulu, Krishnna veni, Dr. K.Srinivasa Rao and Dr.A.VinayaBabu, “Low Power
Design Techniques of CMOS Digital Circuits”, International Journal of Electronics and
Communication Engineering &Technology (IJECET), Volume 3, Issue 2, 2012,
pp. 199 - 208, ISSN Print: 0976- 6464, ISSN Online: 0976 –6472.