The emergence of new hardware and platforms has led to reconsideration of how data management systems are designed. However, certain basic functions such as key indexed access to records remain essential. While we exploit the common architectural layering of prior systems, we make radically new design decisions about each layer. Our new form of B-tree, called the Bw-tree achieves its very high performance via a latch-free approach that effectively exploits the processor caches of modern multi-core chips. Our storage manager uses a unique form of log structuring that blurs the distinction between a page and a record store and works well with flash storage. This paper describes the architecture and algorithms for the Bw-tree, focusing on the main memory aspects. The paper includes results of our experiments that demonstrate that this fresh approach produces outstanding performance.

1. The Bw-Tree
A B-tree for New Hardware Platforms
Presented by Liming Deng

2. Part I - Introduction

3. The New Environment
1. Multi-core CPU
2. Flash storage

4. The New Environment
Multi-core CPU
1. Latch-free
2. Cache-friendly

5. The New Environment
Flash storage ( Providing FTL)
1. Host log structuring for itself

6. Part II - Architecture

7. Architecture
1. Focus on Bw-tree layer
2. Compare to other in-memory index structure

8. Architecture
1. Latch-free
a. Install state via CAS
2. Cache-friendly
a. Delta update
put(x, a):
v = read(x)
return v == cas(x, v, a)

9. Part II - IN-MEMORY
LATCH FREE PAGES

10. IN-MEMORY LATCH FREE
PAGES
Elastic Virtual Pages
LPID PTR
P Memory
Address
Q Flash Offset
Node
Internal index:
Separator key
Record or
Memory pointer to other
PID

11. IN-MEMORY LATCH FREE
PAGES
Updates
1. Create a `update delta record`.
2. Use CAS to prepend `update delta` to Page P.
3. Use CAS to install the memory address of D to
mapping table.

12. IN-MEMORY LATCH FREE
PAGES
Consolidation
1. Apply delta to base page P
2. Use CAS to install new page P’ to mapping table.
How to search?
1. Traverse the delta chain
2. Not found? Go for the base page via a binary search.

13. IN-MEMORY LATCH FREE
PAGES
Garbage Collection
1. Using Epoch-based reclamation: https://aturon.github.io/blog/2015/08/27/epoch/#epoch-based-reclamation
1. A global epoch counter (taking on
values 0, 1, and 2);
2. A global list of garbage for each
epoch;
3. An “active” flag for each thread;
4. An epoch counter for each thread.

14. Part III - SMO

15. SMO =
structure modification operation
Split
1. Child Split
2. Parent Update

16. SMO =
structure modification operation
Split
1. Child Split
a. Create right sibling Q
with Kp

17. SMO =
structure modification operation
Split
1. Child Split
a. Create sibling Q
b. Install split delta.
Split delta = {
Kp, AddressOfQ
}

18. SMO =
structure modification operation
Split
1. Child Split
a. Create sibling Q
b. Install split delta.
2. Parent update
a. Install index entry delta

19. SMO =
structure modification operation
Split
1. Child Split
a. Create sibling Q
b. Install split delta.
2. Parent update
a. Install index entry delta

20. SMO =
structure modification operation
Merge
1. Mark for delete: remove node delta
for R
2. Merging Children: merge delta for L
3. Parent Update.
a. index term delete delta

21. Last Part - Performance

22. Cache

23. Throughput

24. Thank You !