Harmonic optimizer

1. 1/16
AN1616
APPLICATION NOTE
November 2002
Introduction: a little theory
THD (Total Harmonic Distortion) is a convenient way of specifying how much a periodic waveform strays
from a sinusoid with just a number. Mathematically:
,
where An is the RMS amplitude of the nth
(n=1,2,…) harmonic component of the waveform, according to
Fourier's analysis, and ARMS is the overall effective amplitude. In other words, it is the ratio of the energy
associated to higher order harmonics (n>1) to the energy of the fundamental component (n=1), which has
the same frequency as the waveform under consideration. THD is often expressed in %.
Figure 1. Vector diagram and fundamental relationships between quantities involved in PFC
The above definition is obviously applicable to any waveforms, however it makes much sense to invoke
THD when the waveform is supposed to be close to a sinusoid. Such is the case of the current drawn from
the mains by a PFC pre-regulator and its THD may be used as an indicator of how well the pre-regulator
is performing.
THD
An
2
n 2
=
∞
∑
A1
----------------------
-
ARMS
2
A1
2
–
A1
--------------------------------
= =
ϕ1
θ
F = Fundamental App. Power
Q = Reactive Power
A
=
Total Apparent Power
P = Active (Real) Power
D
=
D
is
to
rt
io
n
P
o
w
e
r
Note: for sinusoidal voltage the
same vectors represent currents
2
2
Q
P
F +
=
2
2
D
F
A +
=
θ
=
= tan
F
D
THD
θ
ϕ
=
= cos
cos
A
P
PF 1
by Claudio Adragna
THD-OPTIMIZER CIRCUITS FOR PFC PRE-REGULATORS
Although THD (Total Harmonic Distortion) is not explicitly considered in IEC 61000-3-2 standards, nei-
ther it needs to be very low in order for a piece of equipment to get the presumption of conformity, how-
ever it has become established to require an ultra-low THD in some applications such as electronic
lamp ballast.
This application note, after reviewing some basic theory regarding the main causes of distortion of the
current drawn from the mains by PFC pre-regulators, suggests a couple of simple and inexpensive cir-
cuits that offer significant benefits in terms of THD reduction. The study has been carried out on a TM
(Transition Mode) PFC stage using the L6561 IC and the experimental results are presented.
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2. AN1616 APPLICATION NOTE
2/16
And actually, the real task of PFC pre-regulators is to minimize the THD of the mains current and not max-
imize the Power Factor (PF), in spite of the name. There are at least two good reasons for that.
First, the regulations that a PFC is supposed to help comply with (the well-known IEC 61000-3-2) consider
PF marginally (it is mentioned only to set a limit in class C equipment); rather, they are concerned about
the effective amplitude of each harmonic component. A low THD, although in principle not sufficient to
guarantee that each harmonic falls within its own limit, makes this event practically certain: the distortion
power (refer to fig. 1) is very unlikely to be concentrated on one or few high-order components only, where
the limit is low.
Second, although related to THD, the PF depends also on elements external to the PFC pre-regulator,
such as the capacitors of the input EMI filter. It is quite common, especially at high line and light load, to
achieve an excellent THD and yet measure a PF, though high, not so close to unity as one could expect.
To clarify this point, the diagram and the basic relationships shown in figure 1 can be helpful. After some
trigonometry it is possible to find:
(1)
where ϕ1 is the displacement angle between the input voltage and the fundamental component of the input
current. This relationship is graphically shown in figure 2.
Figure 2. Relationship between THD and PF
It is possible to see that THD degrades very rapidly even with a near unity PF and no phase shift between
line voltage and current (with ϕ1 = 0 and PF=0.98, THD is 20%) and, on the other hand, even with THD=0
the Power Factor can be low anyway, provided there is enough phase shift (with ϕ1 = π/10 rad = 18°, PF
≤ 0.95), like in reactive linear circuits.
PFC pre-regulators introduce no significant phase-shift in the average inductor current, yet it is possible
to see the mains current leading the mains voltage by a phase angle that is as larger as the mains voltage
is higher and/or the output load is lower. This angle is practically ϕ1 (it is true that ϕ1 refers to the first har-
monic only but the mains current is basically first harmonic since a PFC is, by definition, a low-THD sys-
tem).
This phase lead is mostly due to the input EMI filter, always to be used to comply with EMC regulations,
that makes the low frequency impedance of the converter appear capacitive. Note that only the leakage
inductance of the common-mode inductors (and not their self-inductance) or the differential-mode induc-
tors, if used, could give an inductive contribution to the input impedance. This is, however, negligible at
the mains frequency and the effect of the X-caps is by far dominant, whence the phase lead.
With good approximation, then, ϕ1 can be expressed as:
where fL is the mains frequency, Vin the RMS mains voltage and Pin the input power of the PFC pre-reg-
ulator; Cin is the sum of all the X-caps of the EMI filter, plus the capacitor placed after the bridge rectifier,
PF
ϕ1
( )
cos
1 THD
2
+
-----------------------------
-
=
1
0.85
0.90
0.95
PF
0 10 20 30 40 50
THD%
ϕ1 = π/20
= π/10
ϕ1
= 0
ϕ1
ϕ1 tan
1
–
2πfLRinCin
( )
≈ tan
1
–
2πfL
Vin
2
Pin
-------
-Cin
 
 
 
,
=
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3. 3/16
AN1616 APPLICATION NOTE
Cb; is the equivalent large-signal resistance seen from the input of the pre-regulator.
There are two major contributors the THD of PFC pre-regulators. The first one is the so-called "Crossover
Distortion", which shows up as a small plateau (conduction dead-angle) in coincidence to the zero-cross-
ings of the line voltage. The second contributor is the distortion of the current reference generated by the
control IC, which equally reflects on the current drawn from the mains. Both of them will be looked closely.
The X-caps of the EMI filter just divert some mains current, giving origin to the voltage-current phase shift, but
do not usually have any significant effect on the mains current distortion, i.e. on the THD, neither on the con-
duction losses of the bridge rectifier. The capacitor after the bridge rectifier Cb, instead, has a twofold role: not
only it contributes to the phase-shift by adding its capacitance to that of the X-caps, but also worsens the THD
by maintaining a residual voltage on the DC side of the bridge rectifier.
There is always a residual voltage across Cb, which increases with larger Cb values, a higher mains voltage and
a lower load (i.e. a higher Rin). This residual voltage reverse-biases the diodes of the bridge rectifier as long as
the instantaneous mains voltage is lower and blocks current flow from the mains. This phenomenon, exactly
identical to that occurring in non-power-factor-corrected systems, gives origin to a small flat portion in the current
waveform, that is to a conduction dead-angle. This will be referred to as the "crossover distortion". This dead-
angle cannot be eliminated completely even with Cb = 0 because of the threshold voltage of the bridge rectifier.
To complete the picture another effect, interacting and often dominant on that of Cb, must be considered.
It is the lack of input-to-output energy transfer close to the zero crossings of the mains voltage. This has
been already discussed in [2] but will be looked more closely here.
Near zero-crossings the energy that can be stored in the boost inductor is very low, not enough to charge
the total capacitance of the drain node Cdrain (basically, MOSFET's Coss, boost inductor's parasitic intraw-
inding capacitance and boost diode's junction capacitance) up to the output voltage Vout. As a result, the
boost diode will not be turned on for a number of switching cycles (see fig. 11) and energy will be confined
in the tank circuit made up of the drain capacitance and the boost inductor. Cb will be discharged at a lower
rate, essentially determined by the losses of the switch and the tank circuit. This can be seen as a sudden
rise of Rin that may cause the flat portion in the current waveform to anticipate and last longer. In figure 3
the two effects are separated and their impact on the voltage across Cb is shown in detail.
With reference to figure 3 (Cdrain=0 curve), the voltage on Cb strays from the ideal haversine when the line
phase angle is θ radians away from π, where:
.
Again with reference to figure 3 (Cdrain=100 pF curve), input-to-output energy transfer is lacking as long as:
,
where L is the inductance of the boost inductor. Solving this inequality for ψ, yields:
.
Figure 3. Voltage on Cb in the neighborhood of a zero-crossing
Rin Vin
2
/Pin
=
θ θ
tan
≈ 2πfLCbRin
=
1
2
--
-L
2
2
------
-
Pin
Vin
-------
- π ψ
–
( )
sin
 
 
 
2
1
2
--
-CdrainVout
2
≤
ψ ψ
sin
VoutVin
2Pin
-------------------
-
Cdrain
2L
----------------
= =
0
20
40
60
80
V(Cb)
2·π·fL·t
ψ
Cdrain = 100 pF
Cdrain = 0
θ
Haversine
π
Cb = 220 nF
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4. AN1616 APPLICATION NOTE
4/16
The voltage on Cb will stray from the haversine slightly after the line phase angle equals π - ψ (the point
marked by the circle), depending on how much Rin increases. If θ>ψ, which happens for large values of
Cb, the energy lack phenomenon is hidden by the effect of the residual voltage on Cb; if ψ>θ, it is the en-
ergy-transfer lack that is dominant and essentially determines the amount of crossover distortion. It is easy
to show that the condition ψ>θ is true as long as Cb fulfills the following inequality:
Approximately, the duration Td of the flat portion around the zero-crossings can be considered equal to:
,
where α (with α = θ or α = ψ, whichever is larger), is assumed as the conduction dead-angle. Figure 4
illustrates the relationship between Td and THD, which, in the range shown (0<Td·fL<0.25), can be approx-
imated by:
.
Figure 4. Contribution of the current flat portion duration to THD
A significant contribution to THD, besides that due to crossover distortion, is also given by the distortion
of the current reference, used for determining either the envelope of the peak inductor current or its low-
frequency average value, depending on the control scheme adopted by the PFC controller.
The current reference is obtained from the rectified mains voltage, properly scaled down, by multiplication
to the error signal of the voltage control loop, for consistency: the higher the mains voltage, the lower the
current reference needs to be, and vice versa in order for the output voltage to be kept constant.
Provided the rectified mains voltage is a perfect haversine, to get an undistorted current reference, the
error signal (i.e. the output of the error amplifier of the PFC controller) must be a DC voltage: any AC com-
ponent, multiplied by the haversine (which is fed into PFC controller's multiplier input, through a resistor
divider) would give origin to higher order harmonic components. This is what actually happens.
As a matter of facts, the output voltage of a PFC stage has a twice-mains-frequency (2·fL) ripple compo-
nent ∆VOUT superimposed on top of the DC regulated value and the error amplifier has a gain, though low,
however not zero at that frequency (G2fL). Hence a portion of that ripple, ∆VCOMP = G2fL ·∆VOUT, will ap-
pear at the error amplifier output, superimposed on top of the DC value VCOMP.
With some simple algebra, it is possible to show that this ripple originates an additional mains-frequency com-
ponent and a third-harmonic component in the current reference, both of amplitude equal to ∆VCOMP/2 and
with the same phase-shift (depending on loop's phase margin) with respect to the mains current. Obviously,
this current reference distortion reflects on the current drawn by the PFC pre-regulator from the mains in the
same way, hence increasing THD.
Cb
Vout
4πfLVin
--------------------
-
Cdrain
2L
----------------
≤
Td
α
2πfL
-----------
-
≈
THD%
950TdfL
5 4TdfL
–
------------------------
≈
THD%
0 0.05 0.10 0.15 0.20
0.1
1
10
100
0.25
Td · fL
0.01
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5. 5/16
AN1616 APPLICATION NOTE
The contribution to THD, with good approximation, is given by:
where VCOMP0 is the error amplifier output for 0 duty cycle (2.5V in the L6561 [1], 1.28V in the L4981 [5]).
Like the THD originated by crossover distortion, also this contribution gets bigger at high input voltage (be-
cause VCOMP gets lower and G2fL increases, thus making ∆VCOMP larger). Lighter loads result in a lower
VCOMP as well, however the ripple at the PFC output, and thereby ∆VCOMP, decrease proportionally. Thus,
ideally, there is no dependence on the load.
Figure 5. Effect of error amplifier output ripple on the current-reference (3rd
harmonic distortion)
An example of the effect of the 3rd
harmonic distortion on the current reference is illustrated in figure 5 (the
THD of the distorted waveform is 8.5%). As previously said, the amplitude of the 2·fL ripple depends on
the gain of the error amplifier at that frequency and, therefore, on how the error amplifier is compensated.
In this respect, the addition of a zero in the error amplifier gain, to improve stability by a larger phase mar-
gin and reduce the tendency to over/undershooting following on step-load changes, flattens out the gain
at 2·fL, whereas the gain obtained with just a single pole is still rolling off at -20 dB/decade. Thus a PFC
pre-regulator compensated for a constant-power load [3] exhibits a THD higher than that of a PFC com-
pensated for a resistive load, with the same crossover frequency.
To get a quantitative idea, let us consider the 2·fL gain of the error amplifier compensated with a single
pole at the origin (one capacitor between E/A input and output); it is approximately given by:
,
where |Ac| is the gain of the boost power stage @f=fc and fc is the open-loop crossover frequency (e.g. 20
Hz). By using a compensation network like that considered in [3], with the zero placed at the crossover
frequency so as to achieve 45° phase margin, the 2·fL gain will be:
.
Considering what the typical values for fc and fL are, G2fL can be about three to four times higher than in
the previous case.
In systems comprising line voltage feedforward (1/V2
correction) to keep the power stage gain constant
over the mains voltage range, the residual 2·fL ripple (∆VFF) superimposed on the DC value (VFF) repre-
senting the RMS line voltage and that is fed into a multiplier input is another source of distortion for the
current reference. This is the case, for instance, of the L4981 [5]. Again with some simple algebraic ma-
nipulations, it is possible to show that this residual ripple originates an additional mains-frequency compo-
nent and a third-harmonic component in the current reference, both of amplitude equal to ∆VFF and in
phase with the mains current. The contribution to THD (which will be summed to that caused by the E/A
THD% 50
VCOMP
∆
VCOMP VCOMP0
–
-----------------------------------------------
-
≈
t
current
reference
undistorted reference
reference distorted
by 3rd harmonic
G2fL
1
2 Ac
------------
-
fc
fL
---
-
≈
G2fL
2
2 Ac
------------
-
≈
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6. AN1616 APPLICATION NOTE
6/16
residual ripple), with good approximation, is given by:
.
In systems working in Transition Mode (TM), like those controlled by the L6561, another non-ideality is
that they do not work exactly on the boundary between Continuous and Discontinuous Conduction Mode,
as as-sumed for the sake of simplicity.They are actually Discontinuous Mode systems because of the
dead time T0 ( in case of optimum ZCD adjustment, see [4]) occurring after inductor's
demagnetization and before MOSFET's turn-on, during which the drain voltage drops to its minimum value
as a result of the boost inductor ringing with the parasitic drain capacitance.
The presence of the dead-time results in a not exactly sinusoidal low-frequency component of the inductor
current even with a perfectly sinusoidal reference. This contribution worsens THD when T0 is not or no
longer negligible as compared to MOSFET's ON-time, that is at light load or when the system is designed
with a low L (i.e. high switching frequency).
Other minor contributions are given by non-idealities present in the system: for example, the voltage offset
of the PWM comparator inside TM PFC controller IC's emphasizes crossover distortion if positive, espe-
cially at light load, where the signal-to-offset ratio is lower.
Need for THD optimization
There is usually plenty of room between the limits to be respected in order for a piece of equipment to pass
the regulatory requirements of IEC 61000-3-2 and the actual harmonic contents resulting from the action
of a PFC pre-regulator.
As a reference, an upgraded version of the 80W wide-range typical application circuit shown in figure 5 of
the L6561 datasheet [1] will be considered. The circuit has been modified according to the recommenda-
tions given in [2]: C1, called Cb in the previous discussion, has been reduced from 1µF to 220 nF, an
STTA106 has been used in place of the BYT13-600 as D1 and the STP8NA50 has been replaced with an
STP8NC50. The electrical schematic is shown in figure 6 and the changes are highlighted by bold italic
characters.
Figure 6. 80W, wide-range L6561-based PFC pre-regulator: electrical schematic
THD% 100
VFF
∆
VFF
-------------
-
≈
T0 π LCdrain
=
8
3
BRIDGE
4 x 1N4007
R9
1.24 MΩ
1%
R10
10 kΩ
1%
C2
22µF
25V
FUSE
4A/250V
R3
240 kΩ
5%
D3
1N4150
D2
1N5248B
R2
100 Ω
5%
12 nF
C6
R1
68 kΩ
5%
T
5
6
L6561 7
2 1
C3 1µF
R5
10 Ω MOS
STP8NC50
4
R7
998 kΩ
1%
C5
47µF
450V
Vo=400V
Po=80W
-
Vac
(85V to 265V)
R6
0.41Ω
1W
R8
6.34 kΩ
1%
+
-
C7
10nF
NTC
C1
0.22 µF
400V
D1 STTA106
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7. 7/16
AN1616 APPLICATION NOTE
Figure 7. 80W, wide-range L6561-based PFC pre-regulator: harmonic measurement (@ 80W, 220 Vac)
Figure 7 shows the harmonic measurement result along with the limits envisaged by IEC 61000-3-2 stan-
dard for both class C and class D equipment and it is possible to see that it is by far within.
With the above-mentioned changes the THD has been reduced by about 10% (@ 220Vac). The design
tips in [2] also make easier to handle a wider input voltage range (e.g. including also the 277 Vac mains)
or a load that can change in a limited interval with acceptable results.
However in some cases, those recommendations cannot be put into practice for some reason or might not
be enough to meet some special design target that, although exceeding regulatory requirements, may be
required to the designer or have become established in some particular area. Additionally, there might be
some special design cases that cannot be handled easily. Typical examples are:
a) In electronic lamp ballast there is a market requirement calling for THD<10% and sometimes less. In
case of multiple lamp supply, low THD is desired even if one or more lamps are disconnected.
b) In some power supplies with wide-range mains operation, presumption of conformity is required not
only at the rated load but in a range (sometimes broad) of load conditions.
c) Some power supplies are specified for a maximum continuous output power and required to deliver
a peak power level, sometimes considerably higher, for a limited time. In this case it makes sense to
require presumption of conformity under the maximum continuous load conditions rather than the
peak load. This is practically equivalent to point b), since the system will be designed for the peak
level, except for the thermal point of view.
THD optimization: the crossover distortion reducer
The first THD-optimizer circuit is shown in figure 8, highlighted by the boxed area. The purpose of this cir-
cuit is to minimize the crossover distortion. It will not give ant benefit against the 3rd
harmonic distortion
caused by the residual 2·fL ripple on the output of the error amplifier, which will be handled by the second
THD optimizer circuit considered in this note. It will also give no aid in counteracting the PF drop at light
load or high line, since this is mostly due to the increase of ϕ1 but, as previously said, this is of little con-
cern.
The idea behind this circuit is to force the system to handle some excess energy near the zero-crossings
so as to meet the double target of minimizing the number of cycles where the energy in the boost inductor
is not passed on to the output and of fully discharging C1. This can be done by artificially increasing the
ON-time of the power switch with either a positive offset on the multiplier input (Pin 3, MULT) or a negative
offset on the current sense input (pin 4, CS). The latter choice has turned out to be more effective [6]. This
circuit will be maximally effective when crossover distortion is mostly due to energy transfer lack, that is
for the case ψ>θ.
Vin = 220 Vac, Pout = 80 W THD = 8.0% PF = 0.980
1 2 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
1
2
5
10
20
50
100
200
500
Harmonic Order [n]
Harmonic Current [mA]
Measurement Class C limits Class D limits
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8. AN1616 APPLICATION NOTE
8/16
Figure 8. 80W, wide-range PFC pre-regulator with crossover distortion reducer: electrical schematic
The 1N4148 and the 10µF cap generate a negative bus proportional to the mains voltage, depending on
the turn ratio of the auxiliary winding of the boost inductor. Then a summing node is created on the current
sense input (pin 4, CS) with a 220Ω resistor between the sense resistor R6 and pin 4 and another resistor
to the negative voltage. This resistor needs to be adjusted experimentally to find the optimum condition.
The fine-tuning will be done at maximum mains voltage, which is usually the worst-case condition, until
the value that provides the minimum THD is found. The offset added in these conditions is typically about
50 mV.
Summarizing the result, the THD reduction offered by the circuit at full load goes from 16% at low mains
(where THD is already very low) to 58% at maximum mains. The improvement at half load is even more
noteworthy, from 30% to 70%, resulting in THD below 5% all over the entire input voltage range both at
full and half load.
The oscilloscope pictures of figure 9 show the mains current and the voltage after the bridge diode (across
C1) in the circuit of figure 6. In figure 10 it is possible to note the effect of the optimizer circuit of figure 8:
the flat portion is much reduced and C1 is nearly fully discharged. The pictures in figures 11 and 12 allow
comparing the behavior near the zero-crossings (note the almost straight mains current, the much longer
ON-time, the negative offset on the current sense and the much fewer cycles where the drain stays below
the output voltage during the OFF-time). Figures 13, 14 and 15 show the improvement in terms of THD
reduction and harmonic contents distribution.
Figure 9. Mains current and voltage on C1 @ 220 Vac: a) Pout= 80 W; b) Pout = 40W (not optimized)
8
3
BRIDGE
4 x 1N4007
R9
1.24 MΩ
1%
C1
0.22 µF
400V
R10
10 kΩ
1%
C2
22µF
25V
FUSE
4A/250V
R3
240 kΩ
5%
D3
1N4150
D2
1N5248B
R2
100 Ω
5%
12 nF
C6
R1
68 kΩ
5%
T
5
6
L6561 7
2 1
C3 1µF
R5
10 Ω MOS
STP8NC50
4
R7
998 kΩ
1%
C5
47µF
450V
Vo=400V
Po=80W
-
Vac
(85V to 265V)
R6
0.41Ω
1W
R8
6.34 kΩ
1%
+
-
C7
10nF
D1 STTA106
NTC
A
A
1N4148
10 µF
35V
220 Ω
1%
110 kΩ 1%
Crossover dist. reducer
Imains
V (C1)
a)
Imains
V (C1)
b)
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9. 9/16
AN1616 APPLICATION NOTE
Figure 10. Mains current and voltage on C1 @ 220 Vac: a) Pout= 80 W; b) Pout = 40W (optimized)
Figure 11. Not optimized zero-crossing @ 220 Vac, 80W: a) Crossover distortion; b) Zoom of a)
Figure 12. Optimized zero-crossing @ 220 Vac, 80W: a) Residual crossover distortion; b) Zoom of a)
Imains
V (C1)
Imains
V (C1)
a) b)
Imains
Vdrain
Vdrain
Vcs
a) b)
Imains
Vdrain
Vdrain
Vcs
a) b)
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10. AN1616 APPLICATION NOTE
10/16
Figure 13. THD measurements at full and half load
Figure 14. Comparison of Harmonic Contents at full load
Figure 15. Comparison of Harmonic Contents at half load
THD optimization: the ripple compensator
The purpose of this second circuit is to minimize the 3rd
harmonic distortion caused by the residual 2·fL
ripple superimposed on the output of the error amplifier. Like the first circuit, it has negligible effect on PF.
The idea behind this circuit is to inject a voltage ripple in the error amplifier that counteracts the one across
the output bulk capacitor of the PFC pre-regulator and coming from the high-side resistor of the output di-
vider. The other sinusoidal-like signal in the circuit is that fed into the multiplier input (Pin 3, MULT) to gen-
erate the sinusoidal current reference, hence it will be used. The circuit, shown in the schematic of figure
16, will be referred to as the "ripple compensator" circuit.
THD vs. Vin @ Pout = 80 W
85 110 135 175 220 265
0
2
4
6
8
10
12
14
Line Voltage [Vac]
THD [%]
O timized Not o timized
THD vs. Vin @ Pout = 40 W
85 110 135 175 220 265
0
2
4
6
8
10
12
14
Line Voltage [Vac]
THD [%]
O timized Not o timized
Harmonic Contents @ Pout = 80 W
(% of fundamental)
(NOT OPTIMIZED)
85 110 135 175 220 265
0
4
8
12
Line Voltage [Vac]
H [%]
Harmonic Contents @ Pout = 80 W
(% of fundamental)
(OPTIMIZED)
85 110 135 175 220 265
0
4
8
12
Line Voltage [Vac]
H [%]
3rd
5th
7th
Others
3rd
5th
7th
Others
3rd
5th
7th
Others
Harmonic Contents @ Pout = 40 W
(% of fundamental)
(NOT OPTIMIZED)
85 110 135 175 220 265
0
4
8
12
Line Voltage [Vac]
H [%]
Harmonic Contents @ Pout = 40 W
% of fundamental
OPTIMIZED
85 110 135 175 220 265
0
4
8
12
Line Voltage [Vac]
H [%]
3rd
5th
7th
Others
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11. 11/16
AN1616 APPLICATION NOTE
Figure 16. 80W, wide-range PFC pre-regulator with both THD-optimizer circuits: electrical schematic
The compensator capacitor, Cc, injects a current 90° out-of-phase with respect to the one coming from the
high-side resistor of the output divider R7. The average value of this additional current is zero, thus the
output voltage setting will not be altered. The purpose of the series resistor is to limit high-frequency cur-
rents that would otherwise find a low-impedance path to pin 2 through Cc and C3, and that could falsely
trigger the dynamic OVP of the L6561, if over 40 µA. The resistor value has little effect on the ripple com-
pensation, provided its impedance is much smaller than that of Cc at the mains frequency (say, less than
1/10). In the specific case, few kΩ were enough to avoid any malfunctioning due to improper OVP activa-
tion and a 22 kΩ resistor has been chosen to have a good safety margin.
Without going into complex calculation to find the optimum value of Cc, that is the one giving the minimum
ripple amplitude at the output of the error amplifier and then the minimum THD, it is reasonable to assume
that the optimum will be achieved when the amplitudes of the injected currents are equal, that is when:
,
which, solved for Ccopt, yields:
.
In the above equations, ∆Vout is the peak amplitude of the 2·fL output ripple and VMULTpk-pk is the peak-
to-valley amplitude of the signal at pin MULT. The calculation will be done at maximum mains voltage
where the loop gain is maximum and the (uncompensated) ripple amplitude is maximum as well.
The experimental results confirm the initial intuitive assumption: selecting the available capacitance stan-
dard value closest to the result of the above calculation gives actually minimum THD.
The ripple compensator circuit can be used both alone and in conjunction with the crossover distortion re-
ducer, as in the schematic of figure 16. Its effect, qualitatively and quantitatively, will not change signifi-
cantly. Note, however, that the ripple compensator circuit has a loading effect on the resistor divider that
feeds pin MULT. Hence, the valley voltage of the multiplier input will be a bit larger, which goes in the same
direction as the crossover distortion reducer. To avoid overcompensation, which would result in small cur-
rent spikes near the zero-crossings at low line, the negative offset provided by the crossover distortion
reducer must be slightly diminished. In the schematic of figure 16 it is possible to notice that the resistor
8
3
BRIDGE
4 x 1N4007
R9
1.24 MΩ
1%
C1
0.22 µF
400V
R10
10 kΩ
1%
C2
22µF
25V
FUSE
4A/250V
R3
240 kΩ
5%
D3
1N4150
D2
1N5248B
R2
100 Ω
5%
12 nF
C6
R1
68 kΩ
5%
T
5
6
L6561 7
2 1
C3 1 µF
R5
10 Ω MOS
STP8NC50
4
R7
998 kΩ
1%
C5
47µF
450V
Vo=400V
Po=80W
-
Vac
(85V to 265V)
R6
0.41Ω
1W
R8
6.34 kΩ
1%
+
-
C7
10nF
D1 STTA106
NTC
A
A
1N4148
10 µF
35V
220 Ω
1%
150 kΩ 1%
Crossover dist. reducer
CC=10 nF
22 kΩ 1%
Ripple compensator
Vout
∆
R7
--------------
- 2πfLCcoptVMULTpk pk
–
=
Ccopt
Vout
∆
2πfLVMULTpk pk
– R7
-------------------------------------------------------
-
=
www.BDTIC.com/ST

12. AN1616 APPLICATION NOTE
12/16
connecting the negative bus to the current sense pin has been increased from 110 to 150 kΩ.
The ripple compensator offers an additional 15-35% THD reduction at full load in the European mains
range while giving little contribution in the US mains range. As a result the THD has been kept below 3%
over the entire mains range.
The oscilloscope picture of figure 18 shows how the ripple at the output of the error amplifier is reduced
by about 60% by the compensator circuit. Figure 19 illustrates THD improvement while figures 20 and 21
show how harmonic component are distributed. All of them are referred to the circuit of figure 16 compared
to that of figure 8.
The effect of the ripple compensator is more apparent when the control loop of a PFC pre-regulator is com-
pensated with a pole-zero couple [3], as shown in the schematic of figure 17. In this case, as previously
said, the 3rd
harmonic contribution to THD is considerably larger, then its mitigation leads to more con-
spicuous results.
Figure 17. 80W PFC pre-regulator with both THD-optimizer circuits and pole-zero loop compensation
In this case, the additional THD reduction by the compensator can be from 20 to 55% at full load, all over
the entire mains range, leading to results very close to those of the system compensated with a single pole
at the origin. Figure 22 shows THD in the circuit of figure 17 with and without the use of the ripple com-
pensator.
Figure 18. L6561 E/A output ripple reduction with the ripple compensator circuit (@ 220 Vac, 80 W)
Crossover dist. reducer
Ripple compensator
8
3
BRIDGE
4 x 1N4007
R9
1.24 MΩ
1%
C1
0.22 µF
400V
R10
10 kΩ
1%
C2
22µF
25V
FUSE
4A/250V
R3
240 kΩ
5%
D3
1N4150
D2
1N5248B
R2
100 Ω
5%
12 nF
C6
R1
68 kΩ
5%
T
5
6
L6561 7
2 1
470 kΩ
R5
10 Ω MOS
STP8NC50
4
R7
998 kΩ
1%
C5
47µF
450V
Vo=400V
Po=80W
-
Vac
(85V to 265V)
R6
0.41Ω
1W
R8
6.34 kΩ
1%
+
-
C7
10nF
D1 STTA106
NTC
A
A
1N4148
10 µF
35V
220 Ω
1%
150 kΩ 1%
10 kΩ
1 µF
CC=10 nF
22 kΩ 1%
not compensated
compensated
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13. 13/16
AN1616 APPLICATION NOTE
Figure 19. THD measurements at full and half load: circuit of fig. 16 vs. circuit of fig. 8
Figure 20. Comparison of Harmonic Contents at full load (circuit of fig. 16 vs. circuit of fig. 8)
Figure 21. Comparison of Harmonic Contents at half load (circuit of fig. 16 vs. circuit of fig. 8)
Figure 22. THD measurements at full and half load: circuit of fig. 17 w and w/o ripple compensator
THD vs. Vin @ Pout = 80 W
85 110 135 175 220 265
0
1
2
3
4
5
Line Voltage [Vac]
THD [%]
Optimized and compensated
Optimized, not compensated
THD vs. Vin @ Pout = 40 W
85 110 135 175 220 265
0
1
2
3
4
5
Line Voltage [Vac]
THD [%]
Optimized and compensated
Optimized, not compensated
Harmonic Contents @ Pout = 80 W
(% of fundamental)
(OPTIMIZED, NOT COMPENSATED)
85 110 135 175 220 265
0
1
2
3
4
Line Voltage [Vac]
H [%]
Harmonic Contents @ Pout = 80 W
(% of fundamental)
(OPTIMIZED AND COMPENSATED)
85 110 135 175 220 265
0
1
2
3
4
Line Voltage [Vac]
H [%]
3rd
5th
7th
Others
3rd
5th
7th
Others
Harmonic Contents @ Pout = 40 W
(% of fundamental)
(OPTIMIZED, NOT COMPENSATED)
85 110 135 175 220 265
0
1
2
3
4
Line Voltage [Vac]
H [%]
Harmonic Contents @ Pout = 40 W
(% of fundamental)
(OPTIMIZED AND COMPENSATED)
85 110 135 175 220 265
0
1
2
3
4
Line Voltage [Vac]
H [%]
3rd
5th
7th
Others
3rd
5th
7th
Others
THD vs. Vin @ Pout = 40 W
(pole-zero voltage loop compensation)
85 110 135 175 220 265
0
1
2
3
4
5
6
Line Voltage [Vac]
THD [%]
Optimized and compensated
Optimized, not compensated
THD vs. Vin @ Pout = 80 W
(pole-zero voltage loop compensation)
85 110 135 175 220 265
0
1
2
3
4
5
6
Line Voltage [Vac]
THD [%]
Optimized and compensated
Optimized, not compensated
www.BDTIC.com/ST

14. AN1616 APPLICATION NOTE
14/16
EMI Filter
All of the measurements have been done connecting the PFC pre-regulator to the AC source through the
EMI filter illustrated in figure 23. This filter, although not tested for compliance with EMC regulations, at-
tenuates the level of high frequency appearing on the mains current waveform that could mislead the mea-
surement system.
Figure 23. EMI filter used for the measurements
Conclusions
Two simple and inexpensive THD-optimizer circuits, the crossover distortion reducer and the ripple com-
pensator, have been presented. They have been applied to an L6561-based PFC pre-regulator and, with
their combined action, the THD has been kept below 3% at full load, all over the input voltage range. Also
at half load the benefit is considerable since the measured THD has been below 5% for any input voltage.
Their usage, although not necessary in a number of applications, can be advantageous in some cases
such as lamp ballast or SMPS where quality requirements call for presumption of conformity on a broad
load range.
REFERENCES
[1] "L6561, Power Factor Corrector" (DATASHEET)
[2] "Design Tips for L6561 Power Factor Corrector in Wide Range" (AN1214)
[3] "Control loop Modeling of L6561-based TM PFC" (AN1089)
[4] "L6561 Enhanced Transition Mode Power Factor Corrector) (AN966)
[5] "L4981, Power Factor Corrector" (DATASHEET)
[6] "Transition Mode Power Factor Correction Device in Switching Power Supplies", STMicroelectronics'
European Patent Application 02425510.1
[7] Nalbant, M. K. "Power Factor Calculations and Measurements", Applied Power Electronics Conference
and Exposition, 1990. APEC '90. Conference Proceedings 1990.
to the AC
source
470 nF
X2
2.2 nF
Y1
27 mH
470 nF
X2 2.2 nF
Y1
to the L6561
board
www.BDTIC.com/ST

15. 15/16
AN1616 APPLICATION NOTE
APPENDIX
Derivation of the THD vs. Td relationship
Following the approach outlined in [7] it is possible to arrive at the following expression of the PF as a func-
tion of the angle φ, which is half the conduction dead-angle defined in this context:
This expression can be re-written entirely in terms of the conduction dead-angle 2φ:
.
Solving eqn. 1 for THD with ϕ1 = 0:
,
substituting the above expression of PF and expressing in percent yields:
.
Figure A1 shows graphically the relationships of PF and THD% vs. the conduction dead-angle 2φ. Note
that these expressions can be applied even to the input current of non-power-factor-corrected AC/DC con-
verters.
Figure A1. Relationships of PF and THD as functions of the conduction dead-angle
The exact expression can be approximated by the following best-fit function:
(see the dotted line in the right diagram of figure A1) that provides less than 2% error in the range 0<2φ<π/2
and less than 10% error in the range 0<2φ<2π/3.
Being 2φ the conduction dead-angle, the duration of the flat portion in the mains current is:
Combining this expression with that of THD% the result is:
PF
π 2φ
– 2φ
sin
–
2π π 2φ
–
( )sin
2
φ
3
2
--
- 2φ
1
2
--
-π φ
–
+
sin
–
----------------------------------------------------------------------------------------------------
-
=
PF
π 2φ
– 2φ
sin
–
π π 2φ
–
( ) 2 2φ
cos
–
( ) 3 2φ
sin
–
[ ]
------------------------------------------------------------------------------------------
-
=
THD
1
PF
2
----------
- 1
–
=
THD% 100 π
π 2φ
–
( ) 2 2
cos φ
–
( ) 3 2φ
sin
–
π 2φ
– 2φ
sin
–
( )
2
-----------------------------------------------------------------------------
- 1
–
=
0
0
0.5
1
PF
π
2φ
π/2
π/4 3π/4
0.75
0.25
THD%
0
10
10
10
π
2φ
π/2
π/4 3π/4
10
10
10
10
-2
4
3
2
0
-1
1
THD%
950
φ
π
--
-
5 4
φ
π
--
-
–
---------------
-
≈
Td
2φ
2πfL
-----------
-
φ
πfL
-------
-
= =
THD%
950TdfL
5 4TdfL
–
------------------------
≈
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16/16
AN1616 APPLICATION NOTE
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