The document summarizes Gary Leonard Dare's presentation on the IP-XACT standard and SPIRIT Consortium. It discusses the SPIRIT Consortium's creation of standards including IP-XACT, its merger with Accellera, and the standardization of IP-XACT as IEEE P1685. It also notes some limitations of IP-XACT including handling external filesets and hierarchical components.
Fusion Compiler is the next-generation RTL-to-GDSII implementation system architected to address the complexities of advanced node designs and deliver up to 20% improved PPA while reducing Time To Results (TTR) by 2X.
The Software Communications Architecture (SCA) 4.0 is a major revision of the standard and is designed to be more scalable, lightweight, and flexible than the current SCA 2.2.2 specification. It is compatible with radio sizes ranging from small, single channel radios to prime-power, multi-channel sets. Importantly the new SCA 4.0 CORBA PSM extends the reach of the standard into DSP and FPGA processing environments more effectively.
In advance of the availability of the next generation of Core Frameworks that will emerge, this presentation shos how SCA 4.0 middleware can be seamlessly used within existing SCA systems for backwards compatibility while offering benefits to new applications and an efficient migration path to full SCA 4.0 compliance.
Fusion Compiler is the next-generation RTL-to-GDSII implementation system architected to address the complexities of advanced node designs and deliver up to 20% improved PPA while reducing Time To Results (TTR) by 2X.
The Software Communications Architecture (SCA) 4.0 is a major revision of the standard and is designed to be more scalable, lightweight, and flexible than the current SCA 2.2.2 specification. It is compatible with radio sizes ranging from small, single channel radios to prime-power, multi-channel sets. Importantly the new SCA 4.0 CORBA PSM extends the reach of the standard into DSP and FPGA processing environments more effectively.
In advance of the availability of the next generation of Core Frameworks that will emerge, this presentation shos how SCA 4.0 middleware can be seamlessly used within existing SCA systems for backwards compatibility while offering benefits to new applications and an efficient migration path to full SCA 4.0 compliance.
High Performance DSP with Xilinx All Programmable Devices (Design Conference ...Analog Devices, Inc.
This session includes a discussion on rapid prototyping concepts using Xilinx All Programmable FPGAs and SoCs with Analog Devices high speed and precision products. Covered in this session will be common use cases for Xilinx devices in DSP applications that interface to high speed analog. An overview will be provided of how Xilinx accelerates development with DSP platforms that can be used to quickly evaluate and prototype systems that include high speed analog, programmable logic, and embedded processing. Also covered will be an introduction to Xilinx’s new Vivado Design Suite development environment that shortens design cycles by providing an IP centric design flow, easy to use design analysis and debug, and high level design flows supporting C/C++ and MATLAB/Simulink.
Device Abstraction in OSGi Based Embedded Systems - Dimitar Valtchevmfrancis
OSGi Community Event 2013 (http://www.osgi.org/CommunityEvent2013/Schedule)
ABSTRACT
OSGi is gaining popularity as enabling technology for building embedded systems in residential, automotive and M2M markets. In all these contexts it is often necessary to communicate with IP and non-IP devices by using various protocols such as Zigbee, ZWave, KNX, EnOcean, etc. In order to provide a convenient programming model suitable for the realization of end-to-end services it is very important to apply an abstraction layer which unifies the work with devices supporting different protocols. A specification work covering this topic has been already started by OSGi Alliance in cooperation with organizations such as HGI, ETSI M2M, BBF and OneM2M.
This presentation comments the existing approaches for the realization of device abstraction in OSGi. Special attention is paid to the requirements making such an abstraction suitable for interactions with cloud based applications and services. A reference architecture based on the experience gained from numerous commercial projects is presented and explained.
SPEAKER BIO
Dr. Dimitar Valtchev is Chief Technology Officer of ProSyst Software. His main technical interests are in the fields of embedded systems, device management and distributed computing.
Recently Dimitar has been involved in numerous residential and automotive projects using the OSGi technology. He believes in the power of open systems/architectures and actively participates in the work of organizations such as HGI and OSGi Alliance.
Dimitar is a senior member of IEEE and holds MS in Electronics, MS in Computer Science and PhD in Electrical Engineers degrees from the Technical University of Sofia.
Design of LDPC Decoder Based On FPGA in Digital Image Watermarking TechnologyTELKOMNIKA JOURNAL
LDPC code and digital image watermarking technology, which is an effective method of digital copyright protection and information security, has been widely used. But this is a multi-disciplinary, multi technology application scheme. In order to realize FPGA design of LDPC decoder in the application scheme, an effective implementation method of digital watermarking application system must be found. In this paper, MATLAB software and Qt development environment are combined to achieve the digital watermarking application software design. It could get real-time input data for the LDPC decoder. Then the hardware of the LDPC decoder is primarily implemented by FPGA in the digital image watermarking system. And the serial port is used to make the output data of the decoder back to computer for verification. Through the simulation results, the Modelsim time simulation diagram is given, and the watermark image compared with the original image is got. The results show that the resource usage of our system is few, and the decoding rate is fast. It has a certain practical value.
Those slides describe digital design using Verilog HDL,
starting with Design methodologies for any digital circuit then difference between s/w (C/C++) and H/w (Verilog) and the most important constructs that let us start hardware design using Verilog HDL.
High Performance DSP with Xilinx All Programmable Devices (Design Conference ...Analog Devices, Inc.
This session includes a discussion on rapid prototyping concepts using Xilinx All Programmable FPGAs and SoCs with Analog Devices high speed and precision products. Covered in this session will be common use cases for Xilinx devices in DSP applications that interface to high speed analog. An overview will be provided of how Xilinx accelerates development with DSP platforms that can be used to quickly evaluate and prototype systems that include high speed analog, programmable logic, and embedded processing. Also covered will be an introduction to Xilinx’s new Vivado Design Suite development environment that shortens design cycles by providing an IP centric design flow, easy to use design analysis and debug, and high level design flows supporting C/C++ and MATLAB/Simulink.
Device Abstraction in OSGi Based Embedded Systems - Dimitar Valtchevmfrancis
OSGi Community Event 2013 (http://www.osgi.org/CommunityEvent2013/Schedule)
ABSTRACT
OSGi is gaining popularity as enabling technology for building embedded systems in residential, automotive and M2M markets. In all these contexts it is often necessary to communicate with IP and non-IP devices by using various protocols such as Zigbee, ZWave, KNX, EnOcean, etc. In order to provide a convenient programming model suitable for the realization of end-to-end services it is very important to apply an abstraction layer which unifies the work with devices supporting different protocols. A specification work covering this topic has been already started by OSGi Alliance in cooperation with organizations such as HGI, ETSI M2M, BBF and OneM2M.
This presentation comments the existing approaches for the realization of device abstraction in OSGi. Special attention is paid to the requirements making such an abstraction suitable for interactions with cloud based applications and services. A reference architecture based on the experience gained from numerous commercial projects is presented and explained.
SPEAKER BIO
Dr. Dimitar Valtchev is Chief Technology Officer of ProSyst Software. His main technical interests are in the fields of embedded systems, device management and distributed computing.
Recently Dimitar has been involved in numerous residential and automotive projects using the OSGi technology. He believes in the power of open systems/architectures and actively participates in the work of organizations such as HGI and OSGi Alliance.
Dimitar is a senior member of IEEE and holds MS in Electronics, MS in Computer Science and PhD in Electrical Engineers degrees from the Technical University of Sofia.
Design of LDPC Decoder Based On FPGA in Digital Image Watermarking TechnologyTELKOMNIKA JOURNAL
LDPC code and digital image watermarking technology, which is an effective method of digital copyright protection and information security, has been widely used. But this is a multi-disciplinary, multi technology application scheme. In order to realize FPGA design of LDPC decoder in the application scheme, an effective implementation method of digital watermarking application system must be found. In this paper, MATLAB software and Qt development environment are combined to achieve the digital watermarking application software design. It could get real-time input data for the LDPC decoder. Then the hardware of the LDPC decoder is primarily implemented by FPGA in the digital image watermarking system. And the serial port is used to make the output data of the decoder back to computer for verification. Through the simulation results, the Modelsim time simulation diagram is given, and the watermark image compared with the original image is got. The results show that the resource usage of our system is few, and the decoding rate is fast. It has a certain practical value.
Those slides describe digital design using Verilog HDL,
starting with Design methodologies for any digital circuit then difference between s/w (C/C++) and H/w (Verilog) and the most important constructs that let us start hardware design using Verilog HDL.
Apache Pulsar Development 101 with PythonTimothy Spann
Apache Pulsar Development 101 with Python PS2022_Ecosystem_v0.0
There is always the fear a speaker cannot make it. So just in case, since I was the MC for the ecosystem track I put together a talk just in case.
Here it is. Never seen or presented.
Inria Tech Talk : RIOT, l'OS libre pour vos objets connectés #IoTStéphanie Roger
Faites communiquer vos objets connectés avec la solution RIOT !
RIOT est un nano système d'exploitation open source, l’équivalent de Linux, pour l’internet des objets. Grâce aux standards de communication qu'il implémente, il vous permettra de développer facilement et de façon pérenne et sécurisée vos applications pour vos objets communicants et embarqués (agriculture connectée, suivi et gestion de bâtiments intelligents, petits automatismes, usine du futur ...).
Inria, l'institut national de recherche dédié au numérique, qui à French Tech Central connecte les entrepreneurs au meilleur de la recherche publique française, est un des membres co-fondateurs de la communauté mondiale des développeurs RIOT.
Spectra Operating Environment (OE) - Setting a new standard for high performance SCA compliant radio development.
A presentation about the SCA Operating Environment, requirements, a business case for COTS OE & an introduction to Spectra OE and its benefits, performance & complementary products.
John Healy
GM, Software Defined Networking Division
Intel Corporation
Plenaries Session
ONS2015: http://bit.ly/ons2015sd
ONS Inspire! Webinars: http://bit.ly/oiw-sd
Watch the talk (video) on ONS Content Archives: http://bit.ly/ons-archives-sd
Interop Tokyo 2014 SDI (Software Defined Infrustructure) ShowCase Seminoar Presentation. The presentation covers Neutron API models (L2/L3 and Advanced Network services), Neutron Icehouse Update and Juno topics.
Summit 16: How to Compose a New OPNFV Solution Stack?OPNFV
This session showcases how a new OPNFV solution stack (a.k.a. ""scenario"") is composed and stood up. We'll use a new solution stack framed around a new software forwarder (""VPP"") provided by the FD.io project as example for this session. The session discusses how an evolution/change of upstream components from OpenStack, OpenDaylight and FFD.io are put in place for the scenario, how installers and tests need to be evolved to allow for integration into OPNFV's continuous integration, deployment and test pipeline.
IETF building block in the LwM2M Ecosystem (IoT World 2017 Workshop)Open Mobile Alliance
This presentation is delivered by Hannes Tschofening, ARM and Co-chair of IETF ACE & OAuth WGs.
IETF has developed a Constrained Application Protocol (CoAP) which is designed to easily translate to HTTP for simplified integration with the web. It is intended for use in resource constrained internet devices. OMA LwM2M uses CoAP as a transport mechanism. In this presentation, our speaker from IETF will provide you with an introduction to CoAP:
● What is CoAP
● How CoAP works
● What other IETF standards are used by LwM2M
● What is next for IETF in this space
International Journal of Computational Engineering Research(IJCER)ijceronline
International Journal of Computational Engineering Research(IJCER) is an intentional online Journal in English monthly publishing journal. This Journal publish original research work that contributes significantly to further the scientific knowledge in engineering and Technology.
International Journal of Computational Engineering Research(IJCER) ijceronline
International Journal of Computational Engineering Research (IJCER) is dedicated to protecting personal information and will make every reasonable effort to handle collected information appropriately. All information collected, as well as related requests, will be handled as carefully and efficiently as possible in accordance with IJCER standards for integrity and objectivity.
A session in the DevNet Zone at Cisco Live, Berlin. Flare allows users with mobile devices to discover and interact with things in an environment. It combines multiple location technologies, such as iBeacon and CMX, with a realtime communications architecture to enable new kinds of user interactions. This session will introduce the Flare REST and Socket.IO API, server, client libraries and sample code, and introduce you to the resources available on DevNet and GitHub. Come visit us in the DevNet zone for a hands-on demonstration.
1. Summary of the IP-XACT
Standard & SPIRIT Consortium
Gary Leonard Dare
Electrical Engineer in Electronics,
Computing, and EDA
présenté à
École Polytechnique,
Université de Montréal
Sept. 2009
All non-published, non-public, non-excerpted content – Copyright Gary Dare
2. Gary Dare - résumé
Education
B.Sc. - Manitoba (Winnipeg)
Ph.D. - Columbia (New York City)
Professional
Nortel: BNR (Toronto), RBN (Montréal)
Motorola Labs (Chicago)
Mentor Graphics Corporation (Portland, OR)
Delegate to SPIRIT Consortium, 2004-09
3. Outline
Overview
SPIRIT Consortium
IP-XACT Overview
IP-XACT Adoption
Post-SPIRIT World
Accellera-SPIRIT Merger
IEEE P1685 Standardization
Further Work
Some IP-XACT Shortcomings
4. Outline II
Sources
Intro to XML, DesignCon 2006 presentation
Organization Overview, July 2007
DAC 2007 presentation
DAC 2008 presentation
DAC 2009 presentation
Public sources (web pages, data sheets, etc.)
http://www.spiritconsortium.org/
http://www.spiritconsortium.org/press/presentations
5. Main Themes
SPIRIT Consortium
Organization
Standards Development
Accellera Merger
IP-XACT
1.2 (RTL)
1.4 (RTL, ESL)
1.5 (IEEE P1685)
Industry Adoption
7. SPIRIT & IP-XACT
SPIRIT Consortium
standards organization
founded 2003 (inc. 2006)
merging with Accellera
IP-XACT
IP meta-data standard (original name: SPIRIT)
XML Schema
based on Platform Express 1.0 XML Schema
(Mentor Graphics; donated 2003)
8. SPIRIT Scope
“Establish a set of IP and tool integration
standards that enable proliferation of IP
reuse through design automation.”
from Accellera-SPIRIT merger announcement
meeting, DAC 2009
http://www.spiritconsortium.org/
9. SPIRIT Standards
IP-XACT
SystemRDL
RDL donation 2006 (Denali)
Release 1.0 (May 2009)
IP Tagging
from VSIA (organization dissolved, 2008)
IPP 1 3.0 Hard IP Tagging (orig. Artisan)
IPP 4 2.0 Soft IP Tagging
Tag reader/writer (orig. Freescale)
18. Use Case for Design
Automation
Use/Support elements of IP-XACT
Import IP Component Libraries
internal, external, 3 rd Party
Export/Transfer Designs
Interconnection of Standard Interfaces
Transaction (ESL) or Signal (RTL)
Execute Generators
functions to access data about components and
designs (TGI)
generator chains to implement methdology
design flows for hardware and/or software
19. Introduction to XML
http://www.spiritconsortium.org/
http://www.spiritconsortium.org/press/presentations
Presentations from DesignCon 2006
Introduction_to_XML.pdf
20. Why Use XML?
An open, machine readable metadata
standard
Maintained by W3C (controls web standards)
http://www.w3c.org
XML enables cross-domain information
processing tools from multiple vendors
storage in ASCII text
data interchange between incompatible systems
Backed by a wealth of tools and support
many libraries and development environments
see Introduction_to_XML.pdf
21. IP-XACT XML Schema
Highlights
Component
VLNV
Design
Channel
Bus and Abstraction Definitions
Generators
Abstractors
signals to/from transactions
XSL Transform
1.2 to 1.4
1.4 to 1.5
22. IP-XACT Component
Component describes an IP Object including
data on:
VLNV
Bus Interfaces
based on Bus and Abstraction Definitions for Standard
Memory Map(s), Address Space(s)
Register Descriptions
Model
Ports – TLM or RTL signals (“wire ports”)
Filesets
all relevant sets of files for models, etc.
ESL, RTL, drivers, boot code, assertions, stimulus, etc.
Can be a leaf or hierarchical component
23. VLNV
VLNV uniquely identifies a component by
specifying: Leon2 UART
— Name <spirit:vendor>spiritconsortium.org</spirit:vendor>
UART Timers
<spirit:library>Leon2</spirit:library> UART
— Version <spirit:name>UART</spirit:name>
V1.0 V1.0
V1.0
<spirit:version>1.2</spirit:version>
— Library
... UART
— Vendor
Lib1 V1.1 Lib2
- or ANY Vendor1
IP-XACT
Object! UART
Vendor2
V1.0
Lib2
from 20061205_IP-XACT_Worked_Examples_V1.2.pps – IP-SOC 2006
24. IP-XACT Design
Design documents a set of Components
and Interconnections
Accompanied by one or more designConfig
XML files
each contains configuration data for
components present in the design file
A design can become a hierarchical
component
must be referenced by an IP-XACT
Component XML file
25. IP-XACT Channel Concept via
Design Example
Simple subsystem: CPU, AHB-APB bus
bridge, 2 peripherals, 2 interconnects
Channels implement interconnections
bus interfaces are mirrors of standard ports
(Mirror-Master, Mirror-Slave)
based on Bus and Abstraction Definitions
i_apbbus
i_leon2Proc i_apbmst MS0 i_UART
i_ahbbus
M MS1 S
S0 M MM0 MS0 S MM
MM1 MS1 MS2
S1
MS3 S
i_timers
from 20061205_IP-XACT_Worked_Examples_V1.2.pps – IP-SOC 2006
26. Bus & Abstraction Definitions
Bus Definition
Identifies a named interconnection standard
e.g., AMBA AHB 2.0; OCP 2.1; IBM CoreConnect
Also extensions
e.g., OCP 2.x Profiles – block data, xbus read, etc.
Abstraction Definition
defines actual ports for an interconnect standard
references Bus Definition's VLNV
up to 1 transaction level definition (TLM/ESL)
up to 1 signal (wire) level definition (RTL)
27. IP-XACT Generator
TGI – Tight Generator Interface API
Independent of vendor and language
Consistent Data Access about an IP
28. A Word on Generators
IP-XACT TGI
General Purpose
Portable
Generator Chains access data according to IP
designer intent (i.e., databook)
Proprietary Generators
Specific to IP provider and/or DE
not usually portable between EDA tools
IP Provider-specific support is selective
recognized by some DE's, ignored by other DE's
Powerful in supporting environment
29. IP-XACT Adoption
Section 3
Initial adoption focus at enterprise level
Large corporations with lots of IP
Great Recession started in late 2007 in the US,
then went Global ...
Pockets not as deep after 2001 tech recession
Slow recovery to 2007 for high technology
Support for IP-XACT initiatives have stalled in many
large companies
e.g., significant layoffs at NXP, ST, Infineon, Freescale, etc.
EDA firms are suffering because their Customers are
suffering (credit crunch)
30. IP Providers
Design IP
ARM
Synopsys
DesignWare
ST*
NXP* (Philips Semiconductor)
Freescale* (Motorola Semiconductor/SPS)
etc.
Verification IP
Synopsys
DesignWare VIP
Yogitech * Distribution Controlled, Not Open Market
etc.
32. DE Common Characteristics
Import components, designs
Recognize bus and abstraction definitions
Export designs and/or hierarchical
components
Packaging – generate IP-XACT XML for IP
40. IEEE P1685 Standardization
Based on IP-XACT 1.5
ratified in June 2009
SystemRDL-compatible Register Data
bug fixes, enhancements (structure, tag names)
For Standardization
NOT for Production
use IP-XACT 1.4 until P1685 1.0
Schedule
Unknown at Present
Last organizing meeting was 4 Oct 2007
http://www.eda.org/spirit-p1685/
Awaiting a re-start ...
On attends le recommencer ...
41. Further Work I
External Filesets
Multiple Models of an IP ...
can appear from Multiple Sources ...
at Different Times!
Carbon C/C++ (TLM) @ T3
Original CPU - RTL Version Management
(ARM, IBM, etc.) @ T1 Mentor Seamless @ T2 Problem for IP-XACT
XML file of the IP ...
42. Further Work II
Hierarchy
hierarchical components composed of lower
level components
designs become IP ... reusable subsystems
Issues
Port Mapping across levels
some ports may not exist in different views of lower
level components!
Mixed Abstraction Levels
Single TLM model == RTL hierarchical component
no access to subcomponents (e.g., VIP probe ... for RTL!)
semantic rules may not be complete for this situation
43. Summary and Epilogue
SPIRIT Consortium had successful 7 years
Created two standards, adopted a third one
IP-XACT gained significant acceptance for IP
reuse in platform-based design
But not wide first generation adoption (recession)
SPIRIT merger with Accellera combines IP
metadata + language standard development
Language users are also IP-XACT adopters
IEEE P1685 standardization based on 1.5
IP-based design & reuse will be even more
important in the coming New Normal
http://www.eetimes.com/hr/ ... for tech news
44. FIN
End ... of the Beginning!
Q&A
Merci!