Summary of the IP-XACT
Standard & SPIRIT Consortium
                    Gary Leonard Dare

               Electrical Engineer in Electronics,
                     Computing, and EDA

                              présenté à
                     École Polytechnique,
                    Université de Montréal
                          Sept. 2009

 All non-published, non-public, non-excerpted content – Copyright Gary Dare
Gary Dare - résumé

 Education
B.Sc. - Manitoba (Winnipeg)
Ph.D. - Columbia (New York City)



 Professional
Nortel: BNR (Toronto), RBN (Montréal)
Motorola Labs (Chicago)
Mentor Graphics Corporation (Portland, OR)
     
         Delegate to SPIRIT Consortium, 2004-09
Outline

    Overview

    SPIRIT Consortium

    IP-XACT Overview

    IP-XACT Adoption

    Post-SPIRIT World
       Accellera-SPIRIT Merger
       IEEE P1685 Standardization
       Further Work
         
             Some IP-XACT Shortcomings
Outline II


    Sources
       Intro to XML, DesignCon 2006 presentation
       Organization Overview, July 2007
       DAC 2007 presentation
       DAC 2008 presentation
       DAC 2009 presentation
       Public sources (web pages, data sheets, etc.)

    http://www.spiritconsortium.org/
       http://www.spiritconsortium.org/press/presentations
Main Themes

    SPIRIT Consortium
       Organization
       Standards Development
       Accellera Merger


    IP-XACT
       1.2 (RTL)
       1.4 (RTL, ESL)
       1.5 (IEEE P1685)
       Industry Adoption
SPIRIT Consortium

    Section 1
SPIRIT & IP-XACT

    SPIRIT Consortium
       standards organization
       founded 2003 (inc. 2006)
       merging with Accellera

    IP-XACT
       IP meta-data standard (original name: SPIRIT)
       XML Schema
       based on Platform Express 1.0 XML Schema
        (Mentor Graphics; donated 2003)
SPIRIT Scope

    “Establish a set of IP and tool integration
    standards that enable proliferation of IP
    reuse through design automation.”
       from Accellera-SPIRIT merger announcement
        meeting, DAC 2009


    http://www.spiritconsortium.org/
SPIRIT Standards

    IP-XACT

    SystemRDL
       RDL donation 2006 (Denali)
       Release 1.0 (May 2009)


    IP Tagging
       from VSIA (organization dissolved, 2008)
       IPP 1 3.0 Hard IP Tagging (orig. Artisan)
       IPP 4 2.0 Soft IP Tagging
       Tag reader/writer (orig. Freescale)
SPIRIT Members
SPIRIT Reviewing Members
SPIRIT Organization Structure
SPIRIT Operations: Technical
      Working Groups
IP-XACT Overview

    Section 2
IP-XACT Overview



       'databook'
Use Case for IP Providers
Use Case for Designers
Use Case for Design
                  Automation

    Use/Support elements of IP-XACT
       Import IP Component Libraries
         
             internal, external, 3 rd Party
       Export/Transfer Designs
       Interconnection of Standard Interfaces
         
             Transaction (ESL) or Signal (RTL)
       Execute Generators
         
           functions to access data about components and
           designs (TGI)
         
           generator chains to implement methdology
                 design flows for hardware and/or software
Introduction to XML

    http://www.spiritconsortium.org/
       http://www.spiritconsortium.org/press/presentations
       Presentations from DesignCon 2006
       Introduction_to_XML.pdf
Why Use XML?

    An open, machine readable metadata
    standard
       Maintained by W3C (controls web standards)
       http://www.w3c.org

    XML enables cross-domain information
    processing tools from multiple vendors
       storage in ASCII text
       data interchange between incompatible systems

    Backed by a wealth of tools and support
       many libraries and development environments

                               see Introduction_to_XML.pdf
IP-XACT XML Schema
               Highlights

    Component
       VLNV

    Design

    Channel

    Bus and Abstraction Definitions

    Generators

    Abstractors
       signals to/from transactions

    XSL Transform
       1.2 to 1.4
       1.4 to 1.5
IP-XACT Component

    Component describes an IP Object including
    data on:
       VLNV
       Bus Interfaces
         
             based on Bus and Abstraction Definitions for Standard
       Memory Map(s), Address Space(s)
       Register Descriptions
       Model
         
             Ports – TLM or RTL signals (“wire ports”)
       Filesets
         
           all relevant sets of files for models, etc.
         
           ESL, RTL, drivers, boot code, assertions, stimulus, etc.

    Can be a leaf or hierarchical component
VLNV

    VLNV uniquely identifies a component by
    specifying:                          Leon2 UART
    —   Name             <spirit:vendor>spiritconsortium.org</spirit:vendor>
                                         UART         Timers
                         <spirit:library>Leon2</spirit:library>             UART
    —   Version          <spirit:name>UART</spirit:name>
                                       V1.0         V1.0
                                                                               V1.0
                         <spirit:version>1.2</spirit:version>
    —   Library
                         ...                   UART
    —   Vendor
                                     Lib1        V1.1                          Lib2

    - or ANY                                                      Vendor1
    IP-XACT
    Object!                               UART
                           Vendor2
                                            V1.0

                                            Lib2
        from 20061205_IP-XACT_Worked_Examples_V1.2.pps – IP-SOC 2006
IP-XACT Design

    Design documents a set of Components
    and Interconnections

    Accompanied by one or more designConfig
    XML files
       each contains configuration data for
        components present in the design file

    A design can become a hierarchical
    component
       must be referenced by an IP-XACT
        Component XML file
IP-XACT Channel Concept via
      Design Example

    Simple subsystem: CPU, AHB-APB bus
    bridge, 2 peripherals, 2 interconnects

    Channels implement interconnections
        bus interfaces are mirrors of standard ports
         (Mirror-Master, Mirror-Slave)
        based on Bus and Abstraction Definitions
                                                i_apbbus
i_leon2Proc                       i_apbmst            MS0           i_UART
                  i_ahbbus
                                       M              MS1       S
    S0   M        MM0 MS0         S              MM
                  MM1 MS1                             MS2
    S1
                                                      MS3       S
                                                                i_timers

     from 20061205_IP-XACT_Worked_Examples_V1.2.pps – IP-SOC 2006
Bus & Abstraction Definitions

    Bus Definition
       Identifies a named interconnection standard
         
             e.g., AMBA AHB 2.0; OCP 2.1; IBM CoreConnect
       Also extensions
         
             e.g., OCP 2.x Profiles – block data, xbus read, etc.

    Abstraction Definition
       defines actual ports for an interconnect standard
         
             references Bus Definition's VLNV
       up to 1 transaction level definition (TLM/ESL)
       up to 1 signal (wire) level definition (RTL)
IP-XACT Generator

    TGI – Tight Generator Interface API

    Independent of vendor and language

    Consistent Data Access about an IP
A Word on Generators

    IP-XACT TGI
       General Purpose
       Portable
       Generator Chains access data according to IP
        designer intent (i.e., databook)

    Proprietary Generators
       Specific to IP provider and/or DE
         
           not usually portable between EDA tools
         
           IP Provider-specific support is selective
                recognized by some DE's, ignored by other DE's
       Powerful in supporting environment
IP-XACT Adoption

    Section 3

    Initial adoption focus at enterprise level
       Large corporations with lots of IP
       Great Recession started in late 2007 in the US,
        then went Global ...
         
           Pockets not as deep after 2001 tech recession
         
           Slow recovery to 2007 for high technology
         
           Support for IP-XACT initiatives have stalled in many
           large companies
                 e.g., significant layoffs at NXP, ST, Infineon, Freescale, etc.
         
             EDA firms are suffering because their Customers are
             suffering (credit crunch)
IP Providers

    Design IP
       ARM
       Synopsys
         
             DesignWare
       ST*
       NXP* (Philips Semiconductor)
       Freescale* (Motorola Semiconductor/SPS)
       etc.

    Verification IP
       Synopsys
         
             DesignWare VIP
       Yogitech              * Distribution Controlled, Not Open Market
       etc.
Design Environments (DE)

    Magillem (Prosilog)

    Duolog – Socrates

    Synopsys – CoreTools (CoreAssembler, etc.)

    CoWare – Platform Architect
       also AMBA Designer (ARM/Axys)

    Denali – Blueprint

    PDTi – SpectaReg, etc. (Vancouver, BC)

    NXP – NxBuilder (internal)
       built on Mentor Graphics Platform Express

    Mentor Graphics
       Platform Express, Perspecta
       HDL Designer IP-XACT Solution
                           see IP-XACT_Adoption_DATE_2007_final.pdf
DE Common Characteristics

    Import components, designs

    Recognize bus and abstraction definitions

    Export designs and/or hierarchical
    components

    Packaging – generate IP-XACT XML for IP
Platform Express




from Rapid Design Creation Using Configurable IP – Actel Niu, Mentor Graphics China
Platform Express Features

    IP-XACT 1.2 (rel. 3.x), 1.4 (rel. 4.0 Beta)

    Drag & Drop Design Assembly
       Correct By Construction

    Interconnection
       scalable interconnection (vendor extension)

    IP Configuration (static, dynamic)

    Generators
       IP-XACT 1.4 TGI
       Native PX (vendor extension)

    Platform Express XML Schema
       vendor extension

    IP Packager (Model Express)
IP-XACT Benefits seen by NXP
Post-SPIRIT World

    Section 4
       Accellera-SPIRIT Merger
       IEEE P1685 Standardization
       Further Work
         
             Some IP-XACT Shortcomings
Accellera
Accellera Achievements
Accellera-SPIRIT Merger
IEEE P1685 Standardization

    Based on IP-XACT 1.5
       ratified in June 2009
       SystemRDL-compatible Register Data
       bug fixes, enhancements (structure, tag names)
       For Standardization
       NOT for Production
         
             use IP-XACT 1.4 until P1685 1.0

    Schedule
       Unknown at Present
       Last organizing meeting was 4 Oct 2007
       http://www.eda.org/spirit-p1685/
       Awaiting a re-start ...
         
             On attends le recommencer ...
Further Work I

    External Filesets
       Multiple Models of an IP ...
       can appear from Multiple Sources ...
       at Different Times!




                                                    Carbon C/C++ (TLM) @ T3


     Original CPU - RTL                                Version Management
     (ARM, IBM, etc.) @ T1   Mentor Seamless @ T2      Problem for IP-XACT
                                                       XML file of the IP ...
Further Work II

    Hierarchy
       hierarchical components composed of lower
        level components
       designs become IP ... reusable subsystems

    Issues
       Port Mapping across levels
         
             some ports may not exist in different views of lower
             level components!
       Mixed Abstraction Levels
         
             Single TLM model == RTL hierarchical component
                 no access to subcomponents (e.g., VIP probe ... for RTL!)
                 semantic rules may not be complete for this situation
Summary and Epilogue

    SPIRIT Consortium had successful 7 years
       Created two standards, adopted a third one
       IP-XACT gained significant acceptance for IP
        reuse in platform-based design
       But not wide first generation adoption (recession)

    SPIRIT merger with Accellera combines IP
    metadata + language standard development
       Language users are also IP-XACT adopters
       IEEE P1685 standardization based on 1.5

    IP-based design & reuse will be even more
    important in the coming New Normal
       http://www.eetimes.com/hr/ ... for tech news
FIN

    End ... of the Beginning!

    Q&A

    Merci!

Spirit20090924poly

  • 1.
    Summary of theIP-XACT Standard & SPIRIT Consortium Gary Leonard Dare Electrical Engineer in Electronics, Computing, and EDA présenté à École Polytechnique, Université de Montréal Sept. 2009 All non-published, non-public, non-excerpted content – Copyright Gary Dare
  • 2.
    Gary Dare -résumé  Education B.Sc. - Manitoba (Winnipeg) Ph.D. - Columbia (New York City)  Professional Nortel: BNR (Toronto), RBN (Montréal) Motorola Labs (Chicago) Mentor Graphics Corporation (Portland, OR)  Delegate to SPIRIT Consortium, 2004-09
  • 3.
    Outline  Overview  SPIRIT Consortium  IP-XACT Overview  IP-XACT Adoption  Post-SPIRIT World  Accellera-SPIRIT Merger  IEEE P1685 Standardization  Further Work  Some IP-XACT Shortcomings
  • 4.
    Outline II  Sources  Intro to XML, DesignCon 2006 presentation  Organization Overview, July 2007  DAC 2007 presentation  DAC 2008 presentation  DAC 2009 presentation  Public sources (web pages, data sheets, etc.)  http://www.spiritconsortium.org/  http://www.spiritconsortium.org/press/presentations
  • 5.
    Main Themes  SPIRIT Consortium  Organization  Standards Development  Accellera Merger  IP-XACT  1.2 (RTL)  1.4 (RTL, ESL)  1.5 (IEEE P1685)  Industry Adoption
  • 6.
  • 7.
    SPIRIT & IP-XACT  SPIRIT Consortium  standards organization  founded 2003 (inc. 2006)  merging with Accellera  IP-XACT  IP meta-data standard (original name: SPIRIT)  XML Schema  based on Platform Express 1.0 XML Schema (Mentor Graphics; donated 2003)
  • 8.
    SPIRIT Scope  “Establish a set of IP and tool integration standards that enable proliferation of IP reuse through design automation.”  from Accellera-SPIRIT merger announcement meeting, DAC 2009  http://www.spiritconsortium.org/
  • 9.
    SPIRIT Standards  IP-XACT  SystemRDL  RDL donation 2006 (Denali)  Release 1.0 (May 2009)  IP Tagging  from VSIA (organization dissolved, 2008)  IPP 1 3.0 Hard IP Tagging (orig. Artisan)  IPP 4 2.0 Soft IP Tagging  Tag reader/writer (orig. Freescale)
  • 10.
  • 11.
  • 12.
  • 13.
  • 14.
  • 15.
  • 16.
    Use Case forIP Providers
  • 17.
    Use Case forDesigners
  • 18.
    Use Case forDesign Automation  Use/Support elements of IP-XACT  Import IP Component Libraries  internal, external, 3 rd Party  Export/Transfer Designs  Interconnection of Standard Interfaces  Transaction (ESL) or Signal (RTL)  Execute Generators  functions to access data about components and designs (TGI)  generator chains to implement methdology  design flows for hardware and/or software
  • 19.
    Introduction to XML  http://www.spiritconsortium.org/  http://www.spiritconsortium.org/press/presentations  Presentations from DesignCon 2006  Introduction_to_XML.pdf
  • 20.
    Why Use XML?  An open, machine readable metadata standard  Maintained by W3C (controls web standards)  http://www.w3c.org  XML enables cross-domain information processing tools from multiple vendors  storage in ASCII text  data interchange between incompatible systems  Backed by a wealth of tools and support  many libraries and development environments see Introduction_to_XML.pdf
  • 21.
    IP-XACT XML Schema Highlights  Component  VLNV  Design  Channel  Bus and Abstraction Definitions  Generators  Abstractors  signals to/from transactions  XSL Transform  1.2 to 1.4  1.4 to 1.5
  • 22.
    IP-XACT Component  Component describes an IP Object including data on:  VLNV  Bus Interfaces  based on Bus and Abstraction Definitions for Standard  Memory Map(s), Address Space(s)  Register Descriptions  Model  Ports – TLM or RTL signals (“wire ports”)  Filesets  all relevant sets of files for models, etc.  ESL, RTL, drivers, boot code, assertions, stimulus, etc.  Can be a leaf or hierarchical component
  • 23.
    VLNV  VLNV uniquely identifies a component by specifying: Leon2 UART — Name <spirit:vendor>spiritconsortium.org</spirit:vendor> UART Timers <spirit:library>Leon2</spirit:library> UART — Version <spirit:name>UART</spirit:name> V1.0 V1.0 V1.0 <spirit:version>1.2</spirit:version> — Library ... UART — Vendor Lib1 V1.1 Lib2 - or ANY Vendor1 IP-XACT Object! UART Vendor2 V1.0 Lib2 from 20061205_IP-XACT_Worked_Examples_V1.2.pps – IP-SOC 2006
  • 24.
    IP-XACT Design  Design documents a set of Components and Interconnections  Accompanied by one or more designConfig XML files  each contains configuration data for components present in the design file  A design can become a hierarchical component  must be referenced by an IP-XACT Component XML file
  • 25.
    IP-XACT Channel Conceptvia Design Example  Simple subsystem: CPU, AHB-APB bus bridge, 2 peripherals, 2 interconnects  Channels implement interconnections  bus interfaces are mirrors of standard ports (Mirror-Master, Mirror-Slave)  based on Bus and Abstraction Definitions i_apbbus i_leon2Proc i_apbmst MS0 i_UART i_ahbbus M MS1 S S0 M MM0 MS0 S MM MM1 MS1 MS2 S1 MS3 S i_timers from 20061205_IP-XACT_Worked_Examples_V1.2.pps – IP-SOC 2006
  • 26.
    Bus & AbstractionDefinitions  Bus Definition  Identifies a named interconnection standard  e.g., AMBA AHB 2.0; OCP 2.1; IBM CoreConnect  Also extensions  e.g., OCP 2.x Profiles – block data, xbus read, etc.  Abstraction Definition  defines actual ports for an interconnect standard  references Bus Definition's VLNV  up to 1 transaction level definition (TLM/ESL)  up to 1 signal (wire) level definition (RTL)
  • 27.
    IP-XACT Generator  TGI – Tight Generator Interface API  Independent of vendor and language  Consistent Data Access about an IP
  • 28.
    A Word onGenerators  IP-XACT TGI  General Purpose  Portable  Generator Chains access data according to IP designer intent (i.e., databook)  Proprietary Generators  Specific to IP provider and/or DE  not usually portable between EDA tools  IP Provider-specific support is selective  recognized by some DE's, ignored by other DE's  Powerful in supporting environment
  • 29.
    IP-XACT Adoption  Section 3  Initial adoption focus at enterprise level  Large corporations with lots of IP  Great Recession started in late 2007 in the US, then went Global ...  Pockets not as deep after 2001 tech recession  Slow recovery to 2007 for high technology  Support for IP-XACT initiatives have stalled in many large companies  e.g., significant layoffs at NXP, ST, Infineon, Freescale, etc.  EDA firms are suffering because their Customers are suffering (credit crunch)
  • 30.
    IP Providers  Design IP  ARM  Synopsys  DesignWare  ST*  NXP* (Philips Semiconductor)  Freescale* (Motorola Semiconductor/SPS)  etc.  Verification IP  Synopsys  DesignWare VIP  Yogitech * Distribution Controlled, Not Open Market  etc.
  • 31.
    Design Environments (DE)  Magillem (Prosilog)  Duolog – Socrates  Synopsys – CoreTools (CoreAssembler, etc.)  CoWare – Platform Architect  also AMBA Designer (ARM/Axys)  Denali – Blueprint  PDTi – SpectaReg, etc. (Vancouver, BC)  NXP – NxBuilder (internal)  built on Mentor Graphics Platform Express  Mentor Graphics  Platform Express, Perspecta  HDL Designer IP-XACT Solution see IP-XACT_Adoption_DATE_2007_final.pdf
  • 32.
    DE Common Characteristics  Import components, designs  Recognize bus and abstraction definitions  Export designs and/or hierarchical components  Packaging – generate IP-XACT XML for IP
  • 33.
    Platform Express from RapidDesign Creation Using Configurable IP – Actel Niu, Mentor Graphics China
  • 34.
    Platform Express Features  IP-XACT 1.2 (rel. 3.x), 1.4 (rel. 4.0 Beta)  Drag & Drop Design Assembly  Correct By Construction  Interconnection  scalable interconnection (vendor extension)  IP Configuration (static, dynamic)  Generators  IP-XACT 1.4 TGI  Native PX (vendor extension)  Platform Express XML Schema  vendor extension  IP Packager (Model Express)
  • 35.
  • 36.
    Post-SPIRIT World  Section 4  Accellera-SPIRIT Merger  IEEE P1685 Standardization  Further Work  Some IP-XACT Shortcomings
  • 37.
  • 38.
  • 39.
  • 40.
    IEEE P1685 Standardization  Based on IP-XACT 1.5  ratified in June 2009  SystemRDL-compatible Register Data  bug fixes, enhancements (structure, tag names)  For Standardization  NOT for Production  use IP-XACT 1.4 until P1685 1.0  Schedule  Unknown at Present  Last organizing meeting was 4 Oct 2007  http://www.eda.org/spirit-p1685/  Awaiting a re-start ...  On attends le recommencer ...
  • 41.
    Further Work I  External Filesets  Multiple Models of an IP ...  can appear from Multiple Sources ...  at Different Times! Carbon C/C++ (TLM) @ T3 Original CPU - RTL Version Management (ARM, IBM, etc.) @ T1 Mentor Seamless @ T2 Problem for IP-XACT XML file of the IP ...
  • 42.
    Further Work II  Hierarchy  hierarchical components composed of lower level components  designs become IP ... reusable subsystems  Issues  Port Mapping across levels  some ports may not exist in different views of lower level components!  Mixed Abstraction Levels  Single TLM model == RTL hierarchical component  no access to subcomponents (e.g., VIP probe ... for RTL!)  semantic rules may not be complete for this situation
  • 43.
    Summary and Epilogue  SPIRIT Consortium had successful 7 years  Created two standards, adopted a third one  IP-XACT gained significant acceptance for IP reuse in platform-based design  But not wide first generation adoption (recession)  SPIRIT merger with Accellera combines IP metadata + language standard development  Language users are also IP-XACT adopters  IEEE P1685 standardization based on 1.5  IP-based design & reuse will be even more important in the coming New Normal  http://www.eetimes.com/hr/ ... for tech news
  • 44.
    FIN  End ... of the Beginning!  Q&A  Merci!