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“POWER ANALYSIS FOR FFT
ARCHITECHTURE”
By;
SIDDHARTHA V
M.Tech in VLSI DESIGN AND EMBEDDED SYSTEMS
1NMIT
OVERVIEW
INTRODUCTION
VARIENTS
ARCHITECHTURE
REQUIREMENTS
SIMULATIONS AND RESULTS
Fourier Transform
They convert a function from one domain to
another with no loss of information
Reduces the number of calculations in a DFT from N2 to NLogN
 First published by Cooley and Tukey in 1965.
converts a function from the time domain to
the frequency domain.
INTRODUCTION
Time Domain and Frequency Domain
Tells us how properties (air pressure in a sound function, for
example) change over time:
Frequency domain:
Tells us how properties (amplitudes) change over
frequencies:
Time Domain
Two variants:
Decimation-in-time (DIT) FFT:
 “Divide and conquer” approach to DFT, based on grouping even and odd
inputs in DFT definition
Butterfly: multiply twiddle factor before add/subtract
Decimation-in-frequency (DIF) FFT:
“Divide and conquer” approach based on grouping even and odd outputs
Butterfly: multiply twiddle factor after add/subtract
Decimation-in-frequency (DIF) FFT:
Decimation-in-time (DIT) FFT:
ARCHITECHTURE
ITIRATIVE ARCHITECHTURE:
One single stage is used for LogN times.
Hardware Efficient
Time taken = (N*LogN) clock cyles.
PIPELINE PARALLEL ARCHITECHTURE:
LogN times different stages are used.
Requires more Hardware.
Time taken = N clock cycles.
REQUIREMENTS
Software:
XILINX VIVADO TOOL
For FFT coding.
MATLAB TOOL
For verification.
Hardware:
Artix 7,FPGA Board
SIMULATION RESULTS
2-POINT FFT
4 POINT
8 POINT
CONCLUSION:
pipelined parallel FFT architecture has been used
which has a lesser power consumption compared to
serial FFT architectures. It also has the advantage of
complete hardware utilization. For verifying and FFT
algorithms written in verilog. Various programming
approaches were understood.
Siddhartha fft pptx
Siddhartha fft pptx
Siddhartha fft pptx

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Siddhartha fft pptx