Digital Electronics

1. Sanjivani Rural Education Society’s
Sanjivani College of Engineering, Kopargaon-423 603
(An Autonomous Institute, Affiliated to Savitribai Phule Pune University, Pune)
NACC ‘A’ Grade Accredited, ISO 9001:2015 Certified
Department of Computer Engineering
(NBA Accredited)
Prof. S.A.Shivarkar
Assistant Professor
E-mail : shivarkarsandipcomp@sanjivani.org.in
Contact No: 8275032712
Subject- Digital Electronics and Data Communication
(CO204)
Unit 2- Combinational Logic Design

2. Multiplexer
• One of the combinational circuit
• Example
• Several input and only one output
• Data on one of the input line is directed to
output line.
• Select lines!!
• It is also called as data selector.
• Fig. shows multiplexer with n input line and one
output line.
• Number of selector lines are m Where n = 2m
• Selector lines select one out of n data sources
and transmitted to single output channel.
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3. 4:1 Multiplexer
• 4 input lines I0 to I3
• 2 selector lines S1 and S0
• Y=S1’S0’I0 + S1’S0I1 + S1S0’I2 + S1S0I3
• Similarly We have 8:1 mux, 16:1 mux..
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Select Inputs Output
S1 S0 Y
0 0 I0
0 1 I1
1 0 I2
1 1 I3

4. 8:1 Multiplexer
• 8 input lines I0 to I7
• 3 selector lines S2, S1 and S0
• Similarly We have 16:1 mux..
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Select Inputs Output
S2 S1 S0 Y
0 0 0 I0
0 0 1 I1
0 1 0 I2
0 1 1 I3
1 0 0 I4
1 0 1 I5
1 1 0 I6
1 1 1 I7

5. Combinational Circuit Design Using Multiplexer
• Advantages:
• Simplification of logic function is not required.
• Minimize IC package count.
• In order to design combinational circuit using Mux
• Either Truth table should be known
• Or one of the standard form of logical expression must be available.
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6. Combinational Logic Design Using Multiplexer
• Implement following function using
mux.
• F(A,B,C) = ∑m(0,1,4,6)
• Solution
• Mux with 3 select line will be required.
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7. Combinational Logic Design Using Multiplexer
• Implement using Mux
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A B C Y
0 0 0 1
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 1

8. Multiplexer Tree
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9. IC 74151
• It is 8:1 multiplexer.
• It can be used as universal
function generator to
generate any logic function of
four variable.
• Two outputs are provided one
is complemented and other is
uncomplemented.
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10. Combinational logic design Using 74151
• Implement using mux.
• F(A,B,C) = ∑m(0,1,2,5)
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11. Demultiplexer
• It performs reverse operation of multiplexer.
• Accept single input and distributes it over
several outputs.
• The select line determines to which output
line input data is to be transmitted.
• Fig. shows Demultiplexer with n output line
and one input line.
• Number of selector lines are m.
• Where n = 2m
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12. 1:2 Demultiplexer
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• 2 output lines
• 1 selector line
• Y0=S’I
• Y1=SI
Output
S (Select) Y0 Y1
0 I 0
1 0 I

13. 1:4 Demultiplexer
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• 4 output lines
• 2 selector line
• Logical expression
for output
Select Output
S1 S0 Y0 Y1 Y2 Y3
0 0 I 0 0 0
0 1 0 I 0 0
1 0 0 0 I 0
1 1 0 0 0 I

14. Combinational logic design Using Demultiplexer
• Demux can also be used to design
combinational circuit.
• Lets design Full subtractor using
demux.
• So D=∑m(1,2,4,7)
• Bout=∑m(1,2,3,7)
• Design on next slide->
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Input Output
A B Bin D Bout
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

15. Combinational logic design Using Demultiplexer
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16. Demultiplexer Tree
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17. Magnitude Comparator
• It compare magnitude of two n bit binary numbers say A and B and
activates one of three outputs A=B, A>B and A<B.
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18. Design 1 bit Comparator
• It will compare two 1 bit number.
19

19. 1 bit Comparator cont..
• Step1:
• Obtain truth table
• Step 2
• From truth table obtain three K
map for 3 output
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Inputs Output
A0 B0 Y0 (A=B) Y1(A<B) Y2(A>B)
0 0 1 0 0
0 1 0 1 0
1 0 0 0 1
1 1 1 0 0

20. 1 bit Comparator cont..
• Step 3: Obtain simplified expression from K map.
• Y0=A0’B0’ + A0B0
• Y1=A0’B0
• Y2=A0B0’
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21. Design 2 bit comparator
• It will compare two 2 bit numbers.
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22. 2 bit comparator cont..
• Step1:
• Obtain truth table
• Step 2
• From truth table obtain 3 K map for 3 output
• Obtain simplified expression from K map.
Note: Left for self exercise
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A1 A0 B1 B0 Y0 (A=B) Y1(A<B) Y2(A>B)
0 0 0 0 1 0 0
0 0 0 1 0 1 0
0 0 1 0 0 1 0
0 0 1 1 0 1 0
0 1 0 0 0 0 1
0 1 0 1 1 0 0
0 1 1 0 0 1 0
0 1 1 1 0 1 0
1 0 0 0 0 0 1
1 0 0 1 0 0 1
1 0 1 0 1 0 0
1 0 1 1 0 1 0
1 1 0 0 0 0 1
1 1 0 1 0 0 1
1 1 1 0 0 0 1
1 1 1 1 1 0 0

23. IC 7485
• It is used to compare two 4 bit
numbers.
• This 16 pin IC.
• Note that circuit has 3 additional
cascade inputs (Pin 2,3,4).
• They are used to connect more than
one 7485 IC to compare numbers
having more than 4 bits.
• But these input have lower priority.
• They decide output only when 4 bit
input fed to this IC is equal.
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24. IC 7485 cont..
• IF A=0011 and B=0001 then
output (A>B Pin no. 5) will be
high and all other outputs will
be low irrespective of the values
appearing on pin 2,3 and 4.
• When IC 7485 is not used in
cascade mode we keep Pin 2,4
at logic 0 and Pin 3 at logic 1.
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25. IC 7485 cont..
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Compare two 8 bit numbers using 7485

26. Encoder
• Encoders convert single active signal
(out of r inputs) into coded binary, s
bit output. (This is normally referred
to as r line to s line encoder)
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27. Design 4 line to 2 line encoder that take 4 line decimal signal and convert it to binary code
Decimal Binary
D3 D2 D1 D0 A B
0 0 0 1 0 0
0 0 1 0 0 1
0 1 0 0 1 0
1 0 0 0 1 1
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28. Decimal to BCD encoder
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• There are ten switches one for each
number from 0 to 9.
• When particular number is to be fed
to the digital circuit in BCD form the
switch corresponding to that number
is pressed.

29. Priority Encoders
• Often encoders are
called as priority
encoders which means
that more than one of
the r input may be
active, in which case
the output pattern
produced is that for the
highest priority input.
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30. Decoder
• A decode is similar to Demultiplexer with one
exception there is no data input.
• It has n input line and maximum 2n output
line.
• Consider decoder in given figure
• It has control inputs A2,A1,A0
• It is called as 1 of 8 decoder because only 1 of 8
output line is high.
• It is called binary to decimal decoder.
• It has 3 input and 8 output so also called as 3 line
to 8 line decoder.
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31. 3 line to 8 line Decoder.
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