Fault Modeling for Verilog Register Transfer Levelidescitation
As the complexity of Very Large Scale Integration
(VLSI) increases, testing becomes tedious. Currently fault
models are used to test digital circuits at gate level or at levels
lower than gate. Modeling faults at these levels, leads to
increase in the design cycle time period. Hence, there is a
need to explore new approaches for modeling faults at higher
levels. This paper proposes fault modeling at the Register
Transfer Level (RTL) for digital circuits. Using this level of
modeling, results are obtained for fault coverage, area and
test patterns. A software prototype, FEVER, has been developed
in C which reads a RTL description and generates two output
files: one a modified RTL with test features and two a file
consisting of set of test patterns. These modified RTL and test
patterns are further used for fault simulation and fault
coverage analysis. Comparison is performed between the RTL
and Gate level modeling for ISCAS benchmarks and the
results of the same are presented. Results are obtained using
Synopsys, TetraMax and it is shown that it is possible to achieve
100% fault coverage with no area overhead at the RTL level
FAULT MODELING OF COMBINATIONAL AND SEQUENTIAL CIRCUITS AT REGISTER TRANSFER ...VLSICS Design
As the complexity of Very Large Scale Integration (VLSI) is growing, testing becomes tedious and tougher. As of now fault models are used to test digital circuits at the gate level or below that level. By using fault models at the lower levels, testing becomes cumbersome and will lead to delays in the design cycle. In addition, developments in deep submicron technology provide an opening to new defects. We must develop efficient fault detection and location methods in order to reduce manufacturing costs and time to market. Thus there is a need to look for a new approach of testing the circuits at higher levels to speed up the design cycle. This paper proposes on Register Transfer Level (RTL) modeling for digital circuits and computing the fault coverage. The result obtained through this work establishes that the fault coverage with the RTL fault model is comparable to the gate level fault coverage.
Fault Modeling for Verilog Register Transfer Levelidescitation
As the complexity of Very Large Scale Integration
(VLSI) increases, testing becomes tedious. Currently fault
models are used to test digital circuits at gate level or at levels
lower than gate. Modeling faults at these levels, leads to
increase in the design cycle time period. Hence, there is a
need to explore new approaches for modeling faults at higher
levels. This paper proposes fault modeling at the Register
Transfer Level (RTL) for digital circuits. Using this level of
modeling, results are obtained for fault coverage, area and
test patterns. A software prototype, FEVER, has been developed
in C which reads a RTL description and generates two output
files: one a modified RTL with test features and two a file
consisting of set of test patterns. These modified RTL and test
patterns are further used for fault simulation and fault
coverage analysis. Comparison is performed between the RTL
and Gate level modeling for ISCAS benchmarks and the
results of the same are presented. Results are obtained using
Synopsys, TetraMax and it is shown that it is possible to achieve
100% fault coverage with no area overhead at the RTL level
FAULT MODELING OF COMBINATIONAL AND SEQUENTIAL CIRCUITS AT REGISTER TRANSFER ...VLSICS Design
As the complexity of Very Large Scale Integration (VLSI) is growing, testing becomes tedious and tougher. As of now fault models are used to test digital circuits at the gate level or below that level. By using fault models at the lower levels, testing becomes cumbersome and will lead to delays in the design cycle. In addition, developments in deep submicron technology provide an opening to new defects. We must develop efficient fault detection and location methods in order to reduce manufacturing costs and time to market. Thus there is a need to look for a new approach of testing the circuits at higher levels to speed up the design cycle. This paper proposes on Register Transfer Level (RTL) modeling for digital circuits and computing the fault coverage. The result obtained through this work establishes that the fault coverage with the RTL fault model is comparable to the gate level fault coverage.
Functional Verification of Large-integers Circuits using a Cosimulation-base...IJECEIAES
Cryptography and computational algebra designs are complex systems based on modular arithmetic and build on multi-level modules where bit-width is generally larger than 64-bit. Because of their particularity, such designs pose a real challenge for verification, in part because large-integer‘s functions are not supported in actual hardware description languages (HDLs), therefore limiting the HDL testbench utility. In another hand, high-level verification approach proved its efficiency in the last decade over HDL testbench technique by raising the latter at a higher abstraction level. In this work, we propose a high-level platform to verify such designs, by leveraging the capabilities of a popular tool (Matlab/Simulink) to meet the requirements of a cycle accurate verification without bit-size restrictions and in multi-level inside the design architecture. The proposed high-level platform is augmented by an assertion-based verification to complete the verification coverage. The platform experimental results of the testcase provided good evidence of its performance and re-usability.
Digital Security by Design: Formal Verification with Broad-Spectrum ANSI-C Re...KTN
KTN ran a collaborators' workshop on 26 September 2019 in London to explain more about the Digital Security by Design Challenge announced by the government.
The Digital Security by Design challenge has been recently announced by the Department for Business, Energy & Industrial Strategy (BEIS). This challenge, amounting to £70 million of government funding over 5 years, was delivered by UK Research and Innovation (UKRI) through the Industrial Strategy Challenge Fund (ISCF).
This Collaborators' Workshop provides an opportunity to hear more details of the challenge and forthcoming competitions.
A Scoping Workshop for this challenge was held on 30th May: http://ow.ly/oz6230pHlGl
Find out more about the Defence and Security Interest Group at https://ktn-uk.co.uk/interests/defence-security
Join the Defence and Security Interest Group at https://www.linkedin.com/groups/8584397 or Follow KTN_UK Defence group on Twitter https://twitter.com/KTNUK_Defence
Bridging Concepts and Practice in eScience via Simulation-driven EngineeringRafael Ferreira da Silva
The CyberInfrastructure (CI) has been the object of intensive research and development in the last decade, re- sulting in a rich set of abstractions and interoperable software implementations that are used in production today for supporting ongoing and breakthrough scientific discoveries. A key challenge is the development of tools and application execution frameworks that are robust in current and emerging CI configurations, and that can anticipate the needs of upcoming CI applications. This paper presents WRENCH, a framework that enables simulation-driven engineering for evaluating and developing CI application execution frameworks. WRENCH provides a set of high- level simulation abstractions that serve as building blocks for developing custom simulators. These abstractions rely on the scalable and accurate simulation models that are provided by the SimGrid simulation framework. Consequently, WRENCH makes it possible to build, with minimum software development effort, simulators that that can accurately and scalably simulate a wide spectrum of large and complex CI scenarios. These simulators can then be used to evaluate and/or compare alternate platform, system, and algorithm designs, so as to drive the development of CI solutions for current and emerging applications.
Software Architecture: Introduction to the abstraction (May 2014_Split)Henry Muccini
This is an introductory presentation on Software Architecture that I made at the University of Split, in Croatia.
It shows what does it mean abstraction and why it is so important.
ieee projects 2012, ieee 2012 projects, 2012 ieee projects, ieee projects 2012 for it with abstract, ieee projects titles 2012 for it, ieee final year projects 2012 for it
Stay up-to-date on the latest news, events and resources for the OpenACC community. This month’s highlights covers the newly released PGI 19.7, the upcoming 2019 OpenACC Annual Meeting, GPU Bootcamp at RIKEN R-CCS, a complete schedule of GPU hackathons and more!
STATICMOCK : A Mock Object Framework for Compiled Languages ijseajournal
Mock object frameworks are very useful for creating unit tests. However, purely compiled languages lack robust frameworks for mock objects. The frameworks that do exist rely on inheritance, compiler directives, or linker manipulation. Such techniques limit the applicability of the existing frameworks, especially when
dealing with legacy code.
We present a tool, StaticMock, for creating mock objects in compiled languages. This tool uses source-tosource
compilation together with Aspect Oriented Programming to deliver a unique solution that does not rely on the previous, commonly used techniques. We evaluate the compile-time and run-time overhead incurred by this tool, and we demonstrate the effectiveness of the tool by showing that it can be applied to
new and existing code
Functional Verification of Large-integers Circuits using a Cosimulation-base...IJECEIAES
Cryptography and computational algebra designs are complex systems based on modular arithmetic and build on multi-level modules where bit-width is generally larger than 64-bit. Because of their particularity, such designs pose a real challenge for verification, in part because large-integer‘s functions are not supported in actual hardware description languages (HDLs), therefore limiting the HDL testbench utility. In another hand, high-level verification approach proved its efficiency in the last decade over HDL testbench technique by raising the latter at a higher abstraction level. In this work, we propose a high-level platform to verify such designs, by leveraging the capabilities of a popular tool (Matlab/Simulink) to meet the requirements of a cycle accurate verification without bit-size restrictions and in multi-level inside the design architecture. The proposed high-level platform is augmented by an assertion-based verification to complete the verification coverage. The platform experimental results of the testcase provided good evidence of its performance and re-usability.
Digital Security by Design: Formal Verification with Broad-Spectrum ANSI-C Re...KTN
KTN ran a collaborators' workshop on 26 September 2019 in London to explain more about the Digital Security by Design Challenge announced by the government.
The Digital Security by Design challenge has been recently announced by the Department for Business, Energy & Industrial Strategy (BEIS). This challenge, amounting to £70 million of government funding over 5 years, was delivered by UK Research and Innovation (UKRI) through the Industrial Strategy Challenge Fund (ISCF).
This Collaborators' Workshop provides an opportunity to hear more details of the challenge and forthcoming competitions.
A Scoping Workshop for this challenge was held on 30th May: http://ow.ly/oz6230pHlGl
Find out more about the Defence and Security Interest Group at https://ktn-uk.co.uk/interests/defence-security
Join the Defence and Security Interest Group at https://www.linkedin.com/groups/8584397 or Follow KTN_UK Defence group on Twitter https://twitter.com/KTNUK_Defence
Bridging Concepts and Practice in eScience via Simulation-driven EngineeringRafael Ferreira da Silva
The CyberInfrastructure (CI) has been the object of intensive research and development in the last decade, re- sulting in a rich set of abstractions and interoperable software implementations that are used in production today for supporting ongoing and breakthrough scientific discoveries. A key challenge is the development of tools and application execution frameworks that are robust in current and emerging CI configurations, and that can anticipate the needs of upcoming CI applications. This paper presents WRENCH, a framework that enables simulation-driven engineering for evaluating and developing CI application execution frameworks. WRENCH provides a set of high- level simulation abstractions that serve as building blocks for developing custom simulators. These abstractions rely on the scalable and accurate simulation models that are provided by the SimGrid simulation framework. Consequently, WRENCH makes it possible to build, with minimum software development effort, simulators that that can accurately and scalably simulate a wide spectrum of large and complex CI scenarios. These simulators can then be used to evaluate and/or compare alternate platform, system, and algorithm designs, so as to drive the development of CI solutions for current and emerging applications.
Software Architecture: Introduction to the abstraction (May 2014_Split)Henry Muccini
This is an introductory presentation on Software Architecture that I made at the University of Split, in Croatia.
It shows what does it mean abstraction and why it is so important.
ieee projects 2012, ieee 2012 projects, 2012 ieee projects, ieee projects 2012 for it with abstract, ieee projects titles 2012 for it, ieee final year projects 2012 for it
Stay up-to-date on the latest news, events and resources for the OpenACC community. This month’s highlights covers the newly released PGI 19.7, the upcoming 2019 OpenACC Annual Meeting, GPU Bootcamp at RIKEN R-CCS, a complete schedule of GPU hackathons and more!
STATICMOCK : A Mock Object Framework for Compiled Languages ijseajournal
Mock object frameworks are very useful for creating unit tests. However, purely compiled languages lack robust frameworks for mock objects. The frameworks that do exist rely on inheritance, compiler directives, or linker manipulation. Such techniques limit the applicability of the existing frameworks, especially when
dealing with legacy code.
We present a tool, StaticMock, for creating mock objects in compiled languages. This tool uses source-tosource
compilation together with Aspect Oriented Programming to deliver a unique solution that does not rely on the previous, commonly used techniques. We evaluate the compile-time and run-time overhead incurred by this tool, and we demonstrate the effectiveness of the tool by showing that it can be applied to
new and existing code
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1. Insights into SAP testing best practices
2. Heatmap utilization for testing
3. Optimization of testing processes
4. Demo
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Execution from the test manager
Orchestrator execution result
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SAP heatmap example with demo
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Length: 30 minutes
Session Overview
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- What out-of-the-box solutions are available for real-time monitoring JMeter tests?
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Don’t miss this opportunity to elevate your FME expertise and drive your projects to new heights of efficiency.
Essentials of Automations: Optimizing FME Workflows with Parameters
Computational REST Meets Erlang
1. Computational REST Meets Erlang
Alessandro Sivieri Gianpaolo Cugola Carlo Ghezzi
DeepSE Group
Dipartimento di Elettronica e Informazione
Politecnico di Milano
49th International Conference on
Objects, Models, Components and Patterns
June 30, 2011
2. Introduction
The CREST-Erlang architecture
A performance assessment
Conclusions
1 Introduction
2 The CREST-Erlang architecture
3 A performance assessment
4 Conclusions
Sivieri, Cugola, Ghezzi Computational REST Meets Erlang 2/21
3. Introduction
The CREST-Erlang architecture
A performance assessment
Conclusions
Outline
1 Introduction
2 The CREST-Erlang architecture
3 A performance assessment
4 Conclusions
Sivieri, Cugola, Ghezzi Computational REST Meets Erlang 3/21
4. Introduction
The CREST-Erlang architecture
A performance assessment
Conclusions
The scenario
Today’s applications
Large-scale and distributed on the Web
Components running on different devices
Services administered by different organizations
Long time executions, without interruptions or failures
We need frameworks able to
Support scalability and reliability
Guarantee isolation among components
Offer mechanisms for dynamic update of functionalities
Sivieri, Cugola, Ghezzi Computational REST Meets Erlang 4/21
5. Introduction
The CREST-Erlang architecture
A performance assessment
Conclusions
REpresentational State Transfer
The model
Client-server separation for scalability and portability of the
code
Stateless communication for reliability
Caching mechanisms for scalability
The generic interface
Independence of applications on specific services
Application data must be encoded in a standard format
A host may not be able to correctly interpret these data
Sivieri, Cugola, Ghezzi Computational REST Meets Erlang 5/21
6. Introduction
The CREST-Erlang architecture
A performance assessment
Conclusions
REpresentational State Transfer
The model
Client-server separation for scalability and portability of the
code
Stateless communication for reliability
Caching mechanisms for scalability
The generic interface
Independence of applications on specific services
Application data must be encoded in a standard format
A host may not be able to correctly interpret these data
Sivieri, Cugola, Ghezzi Computational REST Meets Erlang 5/21
7. Introduction
The CREST-Erlang architecture
A performance assessment
Conclusions
Computational REST
Designed as a response to real world problems
Adapts REST for an Internet of applications
From a Web of data to a Web of computations
Same REST principles, different key abstraction
Erenkrantz, J.R., Computational REST: a new model for decentralized,
Internet-scale applications, 2009
Sivieri, Cugola, Ghezzi Computational REST Meets Erlang 6/21
8. Introduction
The CREST-Erlang architecture
A performance assessment
Conclusions
Scheme
Proposed as the lingua franca for the Web
Functional language
Native support for continuations
History of uses for mobile code
Drawbacks
No native support for distributed applications
The need to develop many CREST-related concepts (light
processes, communication facilities . . . )
Sivieri, Cugola, Ghezzi Computational REST Meets Erlang 7/21
9. Introduction
The CREST-Erlang architecture
A performance assessment
Conclusions
Scheme
Proposed as the lingua franca for the Web
Functional language
Native support for continuations
History of uses for mobile code
Drawbacks
No native support for distributed applications
The need to develop many CREST-related concepts (light
processes, communication facilities . . . )
Sivieri, Cugola, Ghezzi Computational REST Meets Erlang 7/21
10. Introduction
The CREST-Erlang architecture
A performance assessment
Conclusions
Erlang
Erlang as the lingua franca for the Web
Fault-tolerance and “hot” code update
Distributed applications with an actor-like concurrency model
Design patterns (generic server, supervisor . . . )
Sivieri, Cugola, Ghezzi Computational REST Meets Erlang 8/21
11. Introduction
The CREST-Erlang architecture
A performance assessment
Conclusions
Outline
1 Introduction
2 The CREST-Erlang architecture
3 A performance assessment
4 Conclusions
Sivieri, Cugola, Ghezzi Computational REST Meets Erlang 9/21
12. Introduction
The CREST-Erlang architecture
A performance assessment
Conclusions
Overview
The main architecture
Sivieri, Cugola, Ghezzi Computational REST Meets Erlang 10/21
13. Introduction
The CREST-Erlang architecture
A performance assessment
Conclusions
A service example
1 m y _ s e r v i c e ( S t a t e ) −>
2 receive
3 { Pid , [ {" p a r 1 " , P1} , . . . {" parN " , PN} ] } −>
4 % Do y o u r j o b a c c e s s i n g par1 , . . . parN
%
5 % e v e n t u a l l y c r e a t e a new s t a t e
%
6
7 % I f n e c e s s a r y , spawn m y s e l f on a h o s t
%
8 invoke_spawn ( Hostname , ?MODULE,
9 f u n ( ) −> m y _ s e r v i c e ( NewState )
end ) ,
10
11 % F i n i s h with a t a i l r e c u r s i o n
%
12 m y _ s e r v i c e ( NewState )
13 end .
Sivieri, Cugola, Ghezzi Computational REST Meets Erlang 11/21
14. Introduction
The CREST-Erlang architecture
A performance assessment
Conclusions
So far so good
Full implementation of the Computational REST architectural
style
Erlang is the proposed language of choice for a Web of
computations
Minor development effort
CREST-Erlang prototype outperforms the CREST-Scheme one
Sivieri, Cugola, Ghezzi Computational REST Meets Erlang 12/21
15. Introduction
The CREST-Erlang architecture
A performance assessment
Conclusions
Security concerns
The problem
Mobile code may cause two kinds of problems:
Security of the host with respect to the code
Security of the code with respect to the host
Neither of these have found, as of today, a stable solution.
Sivieri, Cugola, Ghezzi Computational REST Meets Erlang 13/21
16. Introduction
The CREST-Erlang architecture
A performance assessment
Conclusions
CREST security proposals
CREST-Scheme
JVM sandbox (implemented)
Bytecode inspection and self-certifying URLs (ideas)
CREST-Erlang
Trusted network: mutual authentication with SSL.
Sivieri, Cugola, Ghezzi Computational REST Meets Erlang 14/21
17. Introduction
The CREST-Erlang architecture
A performance assessment
Conclusions
CREST security proposals
CREST-Scheme
JVM sandbox (implemented)
Bytecode inspection and self-certifying URLs (ideas)
CREST-Erlang
Trusted network: mutual authentication with SSL.
In both cases they are not enough.
Sivieri, Cugola, Ghezzi Computational REST Meets Erlang 14/21
18. Introduction
The CREST-Erlang architecture
A performance assessment
Conclusions
Outline
1 Introduction
2 The CREST-Erlang architecture
3 A performance assessment
4 Conclusions
Sivieri, Cugola, Ghezzi Computational REST Meets Erlang 15/21
19. Introduction
The CREST-Erlang architecture
A performance assessment
Conclusions
Implementation effort
Stateful and stateless services
Service composition
Framework Framework source code Demo source code
CREST-Scheme 5938 817
CREST-Erlang 2957 768
# of lines of code comparison
Sivieri, Cugola, Ghezzi Computational REST Meets Erlang 16/21
20. Introduction
The CREST-Erlang architecture
A performance assessment
Conclusions
Performances
CREST-Scheme demo performances
(a) Response time (b) Throughput
There is no caching mechanism.
Sivieri, Cugola, Ghezzi Computational REST Meets Erlang 17/21
21. Introduction
The CREST-Erlang architecture
A performance assessment
Conclusions
Performances
Test application performances
(a) Response time (b) Throughput
There is no caching mechanism.
Sivieri, Cugola, Ghezzi Computational REST Meets Erlang 17/21
22. Introduction
The CREST-Erlang architecture
A performance assessment
Conclusions
Outline
1 Introduction
2 The CREST-Erlang architecture
3 A performance assessment
4 Conclusions
Sivieri, Cugola, Ghezzi Computational REST Meets Erlang 18/21
23. Introduction
The CREST-Erlang architecture
A performance assessment
Conclusions
CREST-Erlang
Erlang
Native support for
distribution
concurrency
fault-tolerance
The security problem
Computational REST
A possible evolution addressing the growing presence of
applications interfacing through the Web
Is HTTP the right protocol for transmitting computations?
Sivieri, Cugola, Ghezzi Computational REST Meets Erlang 19/21
24. Introduction
The CREST-Erlang architecture
A performance assessment
Conclusions
CREST-Erlang
Erlang
Native support for
distribution
concurrency
fault-tolerance
The security problem
Computational REST
A possible evolution addressing the growing presence of
applications interfacing through the Web
Is HTTP the right protocol for transmitting computations?
Sivieri, Cugola, Ghezzi Computational REST Meets Erlang 19/21
25. Introduction
The CREST-Erlang architecture
A performance assessment
Conclusions
Future work
Caching mechanism, for improving performances especially for
static content
Introduce the concept of subpeer, part of the latest CREST
definition
Add more security mechanisms, for example for avoiding
possible attacks to a host
Sivieri, Cugola, Ghezzi Computational REST Meets Erlang 20/21
26. Introduction
The CREST-Erlang architecture
A performance assessment
Conclusions
Thank you
Questions?
Sivieri, Cugola, Ghezzi Computational REST Meets Erlang 21/21
27. Appendix
Related works
Dynamic adaptation
Publish-subscribe
Map-reduce
Web applications
REST
Service-Oriented Architecture
Context-oriented languages
ContextErlang
Dynamic Aspect-Oriented Programming
Sivieri, Cugola, Ghezzi Computational REST Meets Erlang 1/4
28. Appendix
Selected bibliography
J.R. Erenkrantz.
Computational REST: a new model for decentralized, Internet-scale
applications.
California State University at Long Beach, 2009.
R.N. Taylor, P. Oreizy and N. Medvidovic.
Runtime software adaptation: framework, approaches, and styles.
ICSE Companion 2008, 899–910, 2008.
J. Armstrong.
Programming Erlang: Software for a Concurrent World.
Pragmatic Bookshelf, 2007.
J. Zachary.
Protecting mobile code in the world.
Internet Computing, IEEE, 7(2):78–82, 2003.
Sivieri, Cugola, Ghezzi Computational REST Meets Erlang 2/4
29. Appendix
Code
The CREST-Erlang code can be found at:
https://github.com/sivieri/crest-erlang
Sivieri, Cugola, Ghezzi Computational REST Meets Erlang 3/4
30. Appendix
Licenses
This presentation is licensed under:
The image on slide 21 can be found at:
www.flickr.com/photos/29890539@N07/4648496819/
Sivieri, Cugola, Ghezzi Computational REST Meets Erlang 4/4