The document describes the clocking subsystem of the PSC9131RDB board. It has two oscillators that provide 100MHz and 66.66MHz clocks. These clocks can be selected and distributed to various clock domains via multiplexers and PLLs. The core, DDR, and DSP clock frequencies are configurable through PLL settings and jumper selections. The board also supports IEEE 1588 timing synchronization and has interfaces to connect two different types of RF modules.

1. PSC9131RDB Reference Manual, Rev. C
Freescale Semiconductor 4-1
4 Functional Description
4.1 Clocking
The following sections describe PSC9131RDB clocking.
Figure 4-1. !)PSC9131RDB Clock Subsystem Block Diagram
Description: The above drawing show the main clocking of the board. The Board has two Clock oscilators
Y3 100Mhz & Y4 66.66Mhz these clocks distrebuted to five mux devices which drive the clocks to the
following clocks: SYSCLK, RTCCLK, TSEC_1588_CLK_IN, DDRCLK & DSP_CLKIN, J16 select
66.66 or 100Mhz for SYSCLK,RTCCLK & TSEC_1588_CLK_IN when J16 is open the input clock
selected is 100Mhz. when J16 is close the selected clock is 66.66Mhz
Note TSEC_1588_CLK_IN is also can its source from the GPS Module clock 10Mhz or from each one of
the RF connectorse.
J12 select the source clock for DDRCLK,when it is open the input clock selected is 100Mhz. when J16 is
close the selected clock is 66.66Mhz
J17 select the source clock for DSP_CLKIN,when it is open the input clock selected is 100Mhz. when J16
is close the selected clock is 66.66Mhz.
PSC9131
SYSCLK
RTCCLK
DDRCLK
DSP_CLKIN
100Mhz
Osc
66.66Mhz
Osc
TSEC_1588_CLK_IN
1
0
1
0
1
0
1
0
1
0
J16
J12
J17
U45
U47
U46
U43
U44
Y3
Y4
J21
J18
00
01
10
11
GPS_10MHZ_CLK
CON1_XCVR_REF
CON2_XCVR_REF
S1
S0
U101
8
7
6
5
4
3
2
1
FLASH_MODE
DDR_SPEED0
DDR_PLL1
DDR_PLL0
SYS_PLL2
SYS_PLL1
ON ’0’ SW1
SYS_PLL0
DDR_SPEED1
OFF ’1’
1K 10K
10K
10K
1K
1K
1K 10K
10K
10K
10K
1K
1K
1K
8
7
6
5
4
3
2
1
IFC_ECC1
IFC_ECC0
DDR H/F MODE
DDR PLL BACKUP
CORE_SPEED
CORE_PLL2
CORE_PLL1
ON ’0’ SW3
CORE_PLL0
OFF ’1’
8
7
6
5
4
3
2
1
ROM_LOC3
ROM_LOC2
ROM_LOC1
ROM_LOC0
DSP_PLL3
DSP_PLL2
DSP_PLL1
ON ’0’ SW4
DSP_PLL0
OFF ’1’
10K
10K
1K
1K
10K
10K
1K
1K
1K 10K
1K
IFC_AD[7]
IFC_ADDR[22]
IFC_ADDR[24]
UART_SOUT[0]
IFC_AD[0]
IFC_AD[1]
IFC_AD[2]
IFC_AD[3]
IFC_AD[4]
IFC_AD[5]
IFC_ADDR[16]
IFC_ADDR[17]
IFC_ADDR[18]
EC_MDC
DSP
PLL
DDR
PLL
CCB
PLL
CCB_CLK
CCB
PLL
CORE_CLK
DDR_CLK
1K
IFC_AD[6]

2. PSC9131RDB Reference Manual, Rev. C
4-2 Freescale Semiconductor
Functional Description
4.1.1 The platform speed (CCB)
is configured by SYS_PLL[0:2] via SW1[1..3] as shown in the drawing above, these configure signals are
sampled on the negation of HRESET on PSC9131 IFC_AD[0:2] signals:
CCB - Clock PLL Platform Ratio
cfg_sys_pll[0:2] - 3’b000 4:1
cfg_sys_pll[0:2]3’b001 5:1 selected for clock in 100Mhz, CCB = 500Mhz.
cfg_sys_pll[0:2]3’b010 6:1 Selected for clock in 66.66Mhz , CCB = 400Mhz Default
cfg_sys_pll[0:2]3’b011 8:1 Reserved
cfg_sys_pll[0:2]3’b100 10:1 Reserved
cfg_sys_pll[0:2]3’b101 12:1 Reserved
cfg_sys_pll[0:2]3’b110 PLL Bypass Functional Mode Reserved
cfg_sys_pll[0:2]3’b111 PLL Bypass Burnin Mode Reserved
4.1.2 DDR Clock
is configured by DDR_PLL[0:1] & DDR_SPEED[0:1] via SW1[4:7] as describe in the DDR block & in
the drawin.
4.1.3 Core clock
is configured by CORE_PLL[0:2] & CORE_SPEED via SW3[1:4] as shown in the drawing above these
configure signals are sampled on the negation of HRESET on PSC9131 IFC_AD[3:6] signals: the
CORE_PLL gets its input clock from the platform clock this clock is multiplying by the value of
cfg_core_pll[0:2]. the CORE_SPEED is a signal that telles the CORE pll its range. in this case the range
is above 500Mhz.
CORE_PLL[0:2]: e500 Core PLL Ratios
cfg_core_pll[0:2]3’b000 Reserved
cfg_core_pll[0:2]3’b001 Reserved
cfg_core_pll[0:2]3’b010 1:1
cfg_core_pll[0:2]3’b011 3:2
cfg_core_pll[0:2]3’b100 2:1 Core freqency 800Mhz = 400 x 2 for clock in 66.66Mhz [default]
cfg_core_pll[0:2]3’b101 5:2 for clock in 66.66Mhz
cfg_core_pll[0:2]3’b110 3:1
cfg_core_pll[0:2]3’b111 Reserved
CORE SPEED: e500 Core Speed
cfg_core_speed1’b0 Core clock frequency is greater than or equal to 333 Mhz and less than 500 Mhz
cfg_core_speed1’b1Core clock frequency is greater than or equal to 500 Mhz and less than 1001 Mhz (default).
4.1.4 DSP Clock
is configured by DSP_PLL[0:3] via SW4[1..4] as shown in the drawing above, these configure signals are
sampled on the negation of HRESET on PSC9131 EC_MDC & IFC_ADDR[16:18] signals:
DSP PLL: DSP Subsystem PLL Configuration
cfg_dsp_pll[0:3]4’b0000 ( 400Mhz) Use COP platform frequency as CLKIN
cfg_dsp_pll[0:3]4’b0001 DSP_CLK = Use 66.66Mhz, DSP Core Frequency =800Mhz (default)
cfg_dsp_pll[0:3]4’b0010 DSP_CLK = Use 100Mhz, DSP Core Frequency = 800Mhz
cfg_dsp_pll[0:3]4’b0011 DSP_CLK = Use 100Mhz, DSP Core Frequency = 1000Mhz
cfg_dsp_pll[0:3]4’b0100, 4’b0101, 4’b0110, 4’b0111, 4’b1000, 4’b1001, 4’b1010, 4’b1011, 4’b1100, 4’b1101, 4’b1110, Reserved
cfg_dsp_pll[0:3]4’b1111 DSP_CLK = Use 66.66Mhz, DSP Core Frequency = 1000Mhz

3. Clocking
PSC9131RDB Reference Manual, Rev. C
Freescale Semiconductor 4-3
4.1.5 DDR
Figure 4-2. DDR Block Diagram
The DDR is 1Gbyte used foure 2Gbit 8bit bus wide devices MT41J256M8HX-15EIT:D from MICRON. The
DDR block gets DDR_CLK —a single ended input clock the input clock can be ether 66.66Mhz or
100Mhz the input clock is selected by J12 if it is open the input clock is 100Mhz if it shorted the frequency
input is 66.66Mhz. the DDR data rate is configured by cfg_ddr_pll [0:1] which sampled at the negaion of
HRESET via signals IFC_AD[7] for cfg_ddr_pll[0] and IFCADDR[22] for cfg_ddr_pll[1] the following
describe the multiplying regarding to the DDR_CLK:
cfg_ddr_pll[0:1] 2’b00 8:1 if the input clock selected 100Mhz this shouls be the default: DDR Block Clock 800Mhz
cfg_ddr_pll[0:1] 2’b01 10:1
cfg_ddr_pll[0:1] 2’b10 12:1 the input clock selected default 66.66Mhz ==> Data Rate 800Mhz (DDR Clock = 400Mhz)
cfg_ddr_pll[0:1] 2’b11 Syncronous Mode Reserved
The cfg_ddr_speed[0:1] are there to determine to the PLL the range of the PLL frequency in this case the
range is bellow 1000Mhz.
4.1.6 Ethernet 1588 Clock
IEEE 1588 compliant time stamping on PSC9131 is accomplished using the per-port transmit time
stamping registers within each Ethernet controller memory space. Transmit Time Stamp Identification
Register & Transmit Time Stamp Register in conjunction with the other common registers, which are
located within the memory space for eTSEC1. Because the common 1588 time stamping registers exist
within the eTSEC1 memory space, the eTSEC1 controller must remain enabled in order to use 1588 time
stamping for any Ethernet port. There is a push in industrial control applications to use Ethernet as the
principal link layer for communications. This requires Ethernet to be used for both data transfer and
real-time control. For real-time systems, each node is required to be synchronized to a master clock. The
precision of this clock is dictated by the application, but generally needs to be of the order of < 1µs for
PSC9131
MDQ[0:31]
MDQS[0:3]
MDQS[0:3]
MDM[0:3]
MBA[0:2]
MA[0:15]
MWE
MCAS
MRAS
MCS0
MCKE0
MCK
MCK
MODT0
MDIC0
MDIC1
MVREF
GVDD
MDQ[0:7]
MDQS
MDQS
MDM
MBA[0:2]
MA[0:15]
MWE
MCAS
MRAS
MCS0
MCKE0
MCK
MCK
MODT0
U93 U87
U92
U95
U97
36.5
ohm
51
ohm
51
ohm
VTT_DDR
VTT_DDR
DUT_GVDD
VREF_DDR
DDR POWER
MC34716EP
Freescale
VTT_DDR VREF_DDR
DUT_GVDD
DUT_GVDD
IN
EN
PG
VCC_5
CORE_POWER_OK
GVDD
DUT_GVDD
U35
DDR_CLK
1
0
J12
U46
66.66Mhz
100Mhz
Y4
Y3
8
7
6
5
4
3
2
1
FLASH_MODE
DDR_SPEED0
DDR_PLL1
DDR_PLL0
SYS_PLL2
SYS_PLL1
ON ’0’ SW1
SYS_PLL0
DDR_SPEED1
OFF ’1’
1K 10K
10K
10K
10K
1K
1K
1K
IFC_AD[7]
IFC_ADDR[22]
IFC_ADDR[24]
UART_SOUT[0]
Default 66Mhz
MT41J256M8HX-15EIT:D
MT41J256M8HX-15EIT:D
MT41J256M8HX-15EIT:D
MT41J256M8HX-15EIT:D

4. PSC9131RDB Reference Manual, Rev. C
4-4 Freescale Semiconductor
Functional Description
high-speed machinery such as printing presses. IEEE 1588 [1588] specifies a mechanism for synchroniz-
ing multiple nodes to a master clock. Support for 1588 can be done entirely in software running on a host
CPU, but applications that require sub 10 µs accuracy need hardware support for accurate time stamping
of incoming packets.The eTSEC includes a new timer clock module to support the IEEE Std. 1588 timer-
standard. The following sections describe the features, programming model, and implementation infor-
mation.IEEE 1588v2 (clock synchronization over Ethernet)
The Tsec_1588_clock in can be sourced by 5 inputs: and selected by 3 jumpers the table bellow describe
the way to configure the TSEC_1588_CLK_IN.
Figure 4-3. Ehernet 1588 & RF Card clocks block
4.1.7 Antena interface
The RDB includes two connectors for monunting two RF boards on it to implement and supports three
industry standard JESD/three custom parallel RF interfaces (two dual and one single port) and three
MAXIM's MaxPHY serial interfaces. The JESD207 standard is supported; other features include the fol-
lowing:
• Supports both full duplex and half duplex modes
TSEC_1588_CLK_IN
J16
J21
J18
GPS_10MHZ_CLK
CON1_XCVR_REF
CON2_XCVR_REF
S1
U101
1
0
U43
00
01
10
11
S0
100Mhz
Osc
66.66Mhz
Osc
Y3
Y4
J6
Pin[61]
J9
Pin[61]
U119
1
0
U65
1
0
U98
MAX_REF_CLK
ADI_REF_CLK
J16
GPS_1PPS_OUTPUT
GPS Module
RF CONN2
RF CONN1
TSEC_1588_TRIG_IN1
PSC9131 U93

5. Clocking
PSC9131RDB Reference Manual, Rev. C
Freescale Semiconductor 4-5
• Supports WCDMA, LTE – FDD, TDD networks
• Support for GSM Sniff
• GPS/1588 based clock correction and timing synchronization
• Air Interface framing and timing control logic
• Dedicated DMA engine for each lane
• Master interface to MAPLE-B2F and CLASS
• Supports 1×, 2×, 4× oversample as needed
• Supports 1T1R, 1T2R, and 2T2r antennas
The RDB support two interface options MAXIM & ADI
4.1.7.1 Maxim PHY Section
The maxim interface is created to support Maxim transceivers using differential TX and RX lines for data
transfer and dedicated SPI3/SPI4 bus for the control. The block diagram below displays the connection
between the PSC9131 and the RF connector 2 which may have the maxim module connected to it.
4.1.7.2 ADI section
The three ANT interfaces are supported on the board through the two connectors 1 & 2. It is expected that
with the RF connectors card. the data send from the 9131 AIC block can be tested.
Figure 4-4. Maxim RF Interface Card Block Diagram
Note: J16 select the MAX_REF_CLK or ADI_REF_CLK, J16: open CON1 supply the clock to
PSC9131
MAX_REF_CLK
MAX_TX_CLK
MAX1_RX_I
MAX1_TX_I
MAX2_RX_I
MAX2_TX_I
MAX3_TX_I
ADI_REF_CLK
ANT1_DIO[0:11]
ANT1_CONTROL
ANT2_DIO[0:11]
ANT2_CONTROL
ANT2_AGC
ANT3_DIO[0:11]
ANT3_CONTROL
ANT3_AGC
ANT3_DO[0:11]
MAX_TX_CLK
MAX1_RX_I
MAX1_TX_I
MAX2_RX_I
MAX2_TX_I
MAX3_TX_I
ANT1_DIO[0:11]
ANT1_CONTROL
ANT2_DIO[0:11]
ANT2_CONTROL
ANT2_AGC
ANT3_DIO[0:11]
ANT3_CONTROL
ANT3_AGC
ANT3_DO[0:11]
CON1_XCVR_REFCON2_XCVR_REF
CON2 CON1
1
0
U65
1
0
J16
I2C1
GPIO RF_ANT_SYNCRF_ANT_SYNC
GPIO RF_RESET_B RF_RESET_B
I2C1(add- I2C10x51 or 0xA2/3) (add - 0x51 or 0xA2/3)
SPI2 SPI2(CS2) SPI2(CS1)
J6 J9
SLIC_SPI1_CS3_B
1
2
3
RFC_SPI1_CS3_B
ANT_TCXO_PWM
J7
1
2
3
J5
CTRL_IN2 1
2
3
J10
CTRL_IN2
VCC_3_3
VCC_5RF
DUT_XVDD
VCC_3_3
VCC_5RF
DUT_XVDD
XCVR_REF_IN_OUT XCVR_REF_IN_OUT
ANT_TCXO_PWM

6. PSC9131RDB Reference Manual, Rev. C
4-6 Freescale Semiconductor
Functional Description
MAX_REF_CLK & CON2 supply clock to ADI_REF_CLK when J16 close CON1 supply
ADI_REF_CLK & CON2 supply the MAX_REF_CLK. If only RF Board is mouted on CON1, for ADI
mode J16 should be close. for MAX mode J16 should be open (CON1 has only ADI mode but it can sup-
ply the clock for MAX_REF_CLK). If only RF Board is mouted on CON2, for ADI mode J16 should be
open. for MAX mode J16 should be close.
For J5, J7, J10 the User should read the RF-Card User Manual.
4.2 RESET and Initialization
A number of modes and features are configurable during HRESET—most are uploaded into the proces-
sor via reset configuration signal pins that are externally driven during HRESET. Some PSC9131RDB
system control signals are described below
Table 4-1. System Control Signals
PSC9131 Signal Name cfg pin name
Default Value -
Switch/Resistor PCA955PW
ANT1_TX_FRAME cfg_test_port_dis Device Default
ANT2_AGC cfg_ddr_half_full_mode SW3[6] ‐ 1 U67 I2C ADDR 27H reg[1] bit[5]
ANT2_TX_FRAME cfg_test_port_mux_sel Device Default
ANT3_AGC cfg_ifc_flash_mode SW1[8] ‐ 0 U60 I2C ADDR 23H reg[0] bit[7]
ANT3_DIO[0] cfg_drowsy_volt Pull Up -1
ANT3_DIO[1] cfg_ppc_drowsy_en Pull Up -1
ANT3_DIO[2] cfg_dsp_drowsy_en Pull Up -1
ANT3_DIO[3] cfg_por_bist Pull Up -1
ANT3_DIO[4] cfg_sb_dis Pull Up -1
ANT3_DIO[5] cfg_fuse_rd_en Device Default
ANT3_DIO[6] cfg_60x Pull Up -1
ANT3_DIO[7] cfg_eng_use[0] Pull Up -1
ANT3_TX_FRAME cfg_eng_use[1] SW5[3] - 1 U86 I2C ADDR 21H reg[0] bit[2]
EC_MDC cfg_dsp_pll[0] SW4[1] - 0 U67 I2C ADDR 27H reg[0] bit[0]
EE1 cfg_svr[1] SW5[2] - 1 U86 I2C ADDR 21H reg[0] bit[1]
HRESET_REQ_B cfg_ddr_pll_backup SW3[5] ‐ 1 U67 I2C ADDR 27H reg[1] bit[4]
IFC_AD[0] cfg_sys_pll[0] SW1[1] ‐ 0 U60 I2C ADDR 23H reg[0] bit[0]
IFC_AD[1] cfg_sys_pll[1] SW1[2] ‐ 1 U60 I2C ADDR 23H reg[0] bit[1]
IFC_AD[2] cfg_sys_pll[2] SW1[3] ‐ 0 U60 I2C ADDR 23H reg[0] bit[2]
IFC_AD[3] cfg_core_pll[0] SW3[1] ‐ 1 U67 I2C ADDR 27H reg[1] bit[0]
IFC_AD[4] cfg_core_pll[1] SW3[2] ‐ 0 U67 I2C ADDR 27H reg[1] bit[1]
IFC_AD[5] cfg_core_pll[2] SW3[3] ‐ 0 U67 I2C ADDR 27H reg[1] bit[2]
IFC_AD[6] cfg_core_speed SW3[4] ‐ 1 U67 I2C ADDR 27H reg[1] bit[3]
IFC_AD[7] cfg_ddr_pll[0] SW1[4] ‐ 1 U60 I2C ADDR 23H reg[0] bit[3]
IFC_ADDR[16] cfg_dsp_pll[1] SW4[2] - 0 U67 I2C ADDR 27H reg[0] bit[1]
IFC_ADDR[17] cfg_dsp_pll[2] SW4[3] - 0 U67 I2C ADDR 27H reg[0] bit[2]
IFC_ADDR[18] cfg_dsp_pll[3] SW4[4] - 1 U67 I2C ADDR 27H reg[0] bit[3]
IFC_ADDR[19] cfg_boot_seq[0] SW2[1] - 1 U60 I2C ADDR 23H reg[1] bit[0]

7. RESET and Initialization
PSC9131RDB Reference Manual, Rev. C
Freescale Semiconductor 4-7
IFC_ADDR[20] cfg_plat_speed SW2[3] - 1 U60 I2C ADDR 23H reg[1] bit[2]
IFC_ADDR[21] cfg_sys_speed SW2[4] - 1 U60 I2C ADDR 23H reg[1] bit[3]
IFC_ADDR[22] cfg_ddr_pll[1] SW1[5] ‐ 0 U60 I2C ADDR 23H reg[0] bit[4]
IFC_ADDR[23] cfg_ifc_pb[0] SW2[5] - 1 U60 I2C ADDR 23H reg[1] bit[4]
IFC_ADDR[24] cfg_ddr_speed[0] SW1[6] ‐ 0 U60 I2C ADDR 23H reg[0] bit[5]
IFC_ADDR[25] cfg_ifc_pb[1] SW2[6] - 1 U60 I2C ADDR 23H reg[1] bit[5]
IFC_ADDR[26] cfg_ifc_pb[2] SW2[7] - 1 U60 I2C ADDR 23H reg[1] bit[6]
IFC_AVD cfg_dram_type Pull Up -1
IFC_CLE cfg_tsec1_prctl Pull Up -1
IFC_OE_B cfg_cpu_boot SW5[4] - 1 U86 I2C ADDR 21H reg[0] bit[3]
IFC_WE_B cfg_ifc_adm_mode SW2[8] - 1 U60 I2C ADDR 23H reg[1] bit[7]
SPI2_MOSI cfg_ifc_ecc[0] SW3[7] ‐ 0 U67 I2C ADDR 27H reg[1] bit[6]
TSEC_1588_PULSE_OUT1 cfg_boot_seq[1] SW2[2] - 1 U60 I2C ADDR 23H reg[1] bit[1]
TSEC1_TXD[0] cfg_rom_loc[0] SW4[5] - 1 U67 I2C ADDR 27H reg[0] bit[4]
TSEC1_TXD[1] cfg_rom_loc[1] SW4[6] - 0 U67 I2C ADDR 27H reg[0] bit[5]
TSEC1_TXD[2] cfg_rom_loc[2] SW4[7] - 0 U67 I2C ADDR 27H reg[0] bit[6]
TSEC1_TXD[3] cfg_rom_loc[3] SW4[8] - 1 U67 I2C ADDR 27H reg[0] bit[7]
UART_RTS_B[1] cfg_svr[0] SW5[1] - 0 U86 I2C ADDR 21H reg[0] bit[0]
UART_SOUT[0] cfg_ddr_speed[1] SW1[7] ‐ 1 U60 I2C ADDR 23H reg[0] bit[6]
UART_SOUT[1] cfg_ifc_ecc[1] SW3[8] ‐ 0 U67 I2C ADDR 27H reg[1] bit[7]

8. PSC9131RDB Reference Manual, Rev. C
4-8 Freescale Semiconductor
Functional Description
Figure 4-5. Power Reset & Reset Configuration Word Block diagram
8
7
6
5
4
3
2
1
FLASH_MODE
DDR_SPEED0
DDR_PLL1
DDR_PLL0
SYS_PLL2
SYS_PLL1
ON ’0’
SYS_PLL0
DDR_SPEED1
OFF ’1’ SW1
8
7
6
5
4
3
2
1
IFC_ADM_MODE
IFC_PB2
IFC_PB0
ON ’0’
IFC_PB1
BOOT_SEQ0
BOOT_SEQ1
PLATE_SPEED
SYS_SPEED
OFF ’1’ SW2
8
7
6
5
4
3
2
1
IFC_ECC1
IFC_ECC0
DDR H/F MODE
DDR PLL BACKUP
CORE_SPEED
CORE_PLL2
CORE_PLL1
ON ’0’
CORE_PLL0
OFF ’1’ SW3
8
7
6
5
4
3
2
1
CPU_BOOT
ENG_USE1
SVR1
ON ’0’
SVR0
OFF ’1’ SW5
1K10K
10K
10K
1K
1K
1K10K
10K
10K
10K
1K
1K
1K
IFC_AD[7]
IFC_ADDR[22]
IFC_ADDR[24]
UART_SOUT[0]
IFC_AD[0]
IFC_AD[1]
IFC_AD[2]
10K
10K
1K
1K
IFC_AD[3]
IFC_AD[4]
IFC_AD[5]
1K
IFC_AD[6]
8
7
6
5
4
3
2
1
ROM_LOC3
ROM_LOC2
ROM_LOC1
ROM_LOC0
DSP_PLL3
DSP_PLL2
DSP_PLL1
ON ’0’ SW4
DSP_PLL0
OFF ’1’
10K
10K
1K
1K
1K 10K
1K
IFC_ADDR[16]
IFC_ADDR[17]
IFC_ADDR[18]
EC_MDC
1K10K
10K
10K
1K
1K
1K10K
10K
10K
10K
1K
1K
1K
10K
10K
1K 10K
10K
10K
1K
1K
1K 10K
10K
10K
10K
10K
1K
1K
10K
1K
10K
10K
1K
1K
1K 10K
1K ANT3_AGC
IFC_ADDR[19]
TSEC_1588_PULSE_OUT1
IFC_ADDR[20]
IFC_ADDR[21]
IFC_ADDR[23]
IFC_ADDR[25]
IFC_ADDR[26]
IFC_WE_B
HRESET_REQ_B
SPI2_MOSI
UART_SOUT[1]
ANT2_AGC
TSEC1_TXD[0]
TSEC1_TXD[1]
TSEC1_TXD[2]
TSEC1_TXD[3]
UART_RTS_B[1]
EE1
ANT3_TX_FRAME
IFC_OE_B
PSC9131
1K
1K
1K
1K
10K
10K
10K
10K
cfg_dram_type IFC_AVD
10K
10K
10K
10K
10K
cfg_tsec1_prctl IFC_CLE
cfg_eng_use[0] ANT3_DIO[7]
ANT3_DIO[6]cfg_60x
cfg_fuse_rd_en ANT3_DIO[5]
ANT3_DIO[4]
cfg_sb_dis
ANT3_DIO[3]
ANT3_DIO[2]
ANT3_DIO[1]
ANT3_DIO[0]cfg_drowsy_volt
cfg_ppc_drowsy_en
cfg_dsp_drowsy_en
cfg_por_bist
ANT2_TX_FRAMEcfg_test_port_mux_sel
ANT1_TX_FRAMEcfg_test_port_dis
10K
10K
10K
10K
Open Drain
MIC2774N-23BM5
nHRESET
HRESET
nHRESET
COP_HRST_B
MIC2774N-23BM5
IN
Powers OK
VCC_1.8V
VCC_3_3
DUT_LVDD
VCC_5
Reset_out
Reset_out
Reset_in
Reset_in
Q
Q D
CK
IN
R
DUT_VDD
en
Core Power
regulator
Q
Q D
CK
R
nHRESET_REQ
HRESET_REQ
PG
HRESET
PO_RESET
SWITCH
SWITCH
PCA9555PW
PCA9555PW
PCA9555PW
I2C ADDRESS 21H
I2C ADDRESS 27H
I2C ADDRESS 23H
I2C16 IO
EXPANDER
EXPANDER
I2C16 IO
EXPANDER
I2C16 IO
U60
U67
U86
I2C
Signals
SD
SC
SD
SC
SD
SC
Connected between switch
Reset Configuration Word
to the Tristete Buffers
See table above
Connected between switch
Reset Configuration Word
to the Tristete Buffers
See table above
Connected between switch
Reset Configuration Word
to the Tristete Buffers
See table above
A
B
C
D
E
F
GHI
G
H
I
A
B
C
D
E
POWER_RESET
E

9. JTAG COP , EONCE Connection & UART.
PSC9131RDB Reference Manual, Rev. C
Freescale Semiconductor 4-9
4.2.1 Power-On-Reset Sequence
The above drawin compose of foure parts:
1. RCW - Reset Configuration words - 36 signals connected to 5 dip swiches each one of them of 8 bits to
configure each one of the 36 pins to high or low to the propriate PSC9131 reset value. connected to a
three state buffers which open during HRESET plus 4 - 8 system clocks. also 12 signals configured to
constant valsue ans shown in the table above!
2. Three IO expander PCA9555PW that connected to the input of the three state buffers, the
PCA9555PW is controlled by I2C bus. each one of the RCW signal can be driven to low or high during
reset. the I2C address is ox21, 0x23 & 0x27.
3. Power On reset and HRESET circuit. It contain two options of board power on and four reset options.
the board power on can be done by SW8 if the user push SW8 the core power is turn off this cause all the
PSC1931 powers to turn off for about 3 second at this time hreset is driven low to the PSC9131and then
turn on the core power when the core power is stable it drive power good to all other PSC9131 power reg-
ulators and turn them on during this time hreset is driven low until all powers are stable. the second way
to power on the is by writing to the PSC9131 HRESET_REQ register. this writing perform the same
sequence as the push botten.
4. The reset sequence diagram it show the flow of the reset circuit.
4.3 JTAG COP , EONCE Connection & UART.
The PSC9131RDB includes two JTAGs: JTAG COP for the power PC and JTAG EONCE for DSP. The
JTAG EONCE is muxed with UART 1. there is a possibility to to control the EONCE via the JTAG COP.
the table bellow describe the way the EONCE & COP are controled.
Table 4-2. JTAG COP & JTAG EONCE
CFG_JTAG_MODE[0:1]
SW6[3,4]
Power Architecture
JTAG Available
DSP Architecture
JTAG Available
JTAG Topology
00 YES NO Access Power Architecture domain and DSP
domain using Power Architecture JTAG port
01 YES NO Access DSP domain using Power Architecture
JTAG port
10 YES NO Access Power Architecture domain using Power
Architecture JTAG port
11 YES YES Access Power Architecture domian using Power
Architecture JTAG and DSP domain using DSP JTAG

10. PSC9131RDB Reference Manual, Rev. C
4-10 Freescale Semiconductor
Functional Description
Figure 4-6. COP EONCE & UART Block Diagram
The above Drawing describe the COP EONCE & UART0 Block diagram. The UART can be operate in
two modes: if DSP JTAG is selected (CFG_JTAG_MODE1(SW6[4]) = 1)then the UART0 use only
TXD & RXD signals. If DSP JTAG is not selected (CFG_JTAG_MODE1(SW6[4]) = 0) UART0 use also
CopConnectorHeaderJ3
1 2
3 4
5 6
7 8
9 10
1112
1314
1516
COP_TRST_B
COP_TDO
COP_TDI
COP_TCLK
COP_TMS
CKSTP_OUT_B
PU_3V3
COP_TRST
COP_HRST
GND
PU_3V3
CKSTP_IN_B
GND
GND
GND
COP_TRST_B
COP_TDO
COP_TDI
COP_TCLK
COP_TMS
CKSTP_OUT_B
COP_TRST
COP_HRST
CKSTP_IN_B
EONCEConnectorHeaderJ2
1 2
3 4
5 6
7 8
9 10
1112
1314
DSP_TDO
DSP_TDI
DSP_TCK
DSP_TMS
DSP_TRST
DSP_HRST
GND
VCC_3V3
GND
1
2
3
4
5
6
7
8
9
OUT
OUT
IN
IN
RS232-Trancesiver
UART0_TXD
UART0_RXD
UART0_CTS
UART0_RTS
IFC_WP_B
POWER_UP_RESET
READY
HRESET&POWER_UP PUSH BUTTONHRESET_B
CFG_JTAG_MODE1(SW6[4])
0
1
0
1
0
1
0
1
DSP_TDO
UART0_CTS/DSP_TMS
UART0_RTS/DSP_TCK
IFC_WP_B/DSP_TDI
READY/DSP_TRST
U10
U61
J25
J3
J2
PSC9131

11. ETHERNET
PSC9131RDB Reference Manual, Rev. C
Freescale Semiconductor 4-11
CTS & RTS, in this case The flash used IFC_WP signals in this case the ready led D14 is light if the core
is in run mode.
Note; HRESET signal is comon to EONCE & COP JTAG, it also gets its signal from power up or hreset
push button.
4.4 ETHERNET
The PSC9131RDB has two Ethernet phys used VTESS single phy VSC8641XKO. the RDB used the
RGMII mode for both phys. the phys configured for address 0b00000 & 0b00011 (0&3).
the following tables describe the default setting of each one of the phys.
Table 4-3. PHY configuration
CMODE[0:4] CODE Bit3 CODE Bit2 CODE Bit1 CODE Bit0
0 PHY addr[0] clockout enable Advertis asymetric puse Advertis asymetric puse
1 PHY addr[1] link speed downshift speed/duplex mode[1] speed/duplex mode[1]
2 PHY addr[2] ACTI-PHY RGMII clock skew[1] RGMII clock skew[0]
3 PHY addr[3] PHY addr[4] MAC Calibration[0] MAC Calibration[1]
4 MAC Mode LED3[1] LED3[0] LED Combine/seperate
Table 4-4. PHY0 default configuration
Resistor
PU/PD
CMODE[0:4] CODE Bit3 CODE Bit2 CODE Bit1 CODE Bit0
PD 12.1K 0 0 clkout en =1 0 1
PD 8.25K 1 0 1 0 0
PD 5.9K 2 0 0 1 1
PD 0K 3 0 0 0 0
PD 2.26K 4 0 0 0 1
Table 4-5. PHY3 default configuration
Resistor
PU/PD
CMODE[0:4] CODE Bit3 CODE Bit2 CODE Bit1 CODE Bit0
PU 2.26K 0 1 clkout en =0 0 1
PU 8.25K 1 1 1 0 0
PD 5.9K 2 0 0 1 1
PD 0K 3 0 0 0 0
PD 2.26K 4 0 0 0 1

12. PSC9131RDB Reference Manual, Rev. C
4-12 Freescale Semiconductor
Functional Description
As it can see in the above tables the difference between the configuration of phy0 & phy3 is the address.
one is address #0 and the other is address #3 also phy address #3 is in default clock out disable, in this
case both eTSEC1 (phy address #0) & eTSEC2 (phy address #3) are using TSEC1_GTX_CLK125. If the
user desire he can configure the phy to enable clkout clock enable and also configure TSEC2 to use
TSEC2_GTX_CLK125. the drawing bellow describe the PSC9131RDB ethernet block diagram.
Figure 4-7. PSC9131RDB Ethernet Block diagram
4.5 SPI
The PSC9131RDB use SPI1 & SPI2.
SPI1 connected to RF connector #2 CS3 via J7 connect J7 1,2 for use it as SPI1_CS3 or for its alternal
function connect J7 2,3 see FR card for more information, also SPI 1 is connected to SLIC Le88266DLC
CS1 and spansion flash S25FL128P0XNFI00 cs0. SPI1_MISO can be use for its alternativ function
CHECK_STOP_IN in 3pin J8 connect J8 1,2 the RDB use the SPI_MISO, J8 connected 2,3 the
check_stop_in function is used on the rdb.
SPI2 connected to RF connector #1 CS0 & CS1 RF connecter #2 CS2 & CS3
Figure 4-8. PSC9131RDB SPI Block diagram
PSC9131 VTESS - VSC8641XKO
U105 PHY ADD0
VTESS - VSC8641XKO
U96 PHY ADD3
MDC
MDIO
MDC
MDIO
MDC
MDIO
RXCLK
RXD[3:0]
RXDV
TSEC1_RXCLK
TSEC1_RXD[3:0]
TSEC1_TSEC1_RXDV
GTXCLK
TXD[3:0]
TXEN
CLKOUT
RXCLK
RXD[3:0]
RXDV
GTXCLK
TXD[3:0]
TXEN
CLKOUT
TSEC1_GTXCLK
TSEC1_TXD[3:0]
TSEC1_TXEN
TSEC1_GTX_125
TSEC2_RXCLK
TSEC2_RXD[3:0]
TSEC2_TSEC1_RXDV
TSEC2_GTXCLK
TSEC2_TXD[3:0]
TSEC2_TXEN
TSEC2_GTX_125
RJ45 P2
RJ45 P3
PSC9131
SPI-1
SPI-2
RF card2
CS3
CS2
CS1
CS0 Spansiom
S25FL128P0XNFI00
ZARLINK
Le88266DLC
RF card1
CS0
CS1
CS2
U68
U84
J6
J9

13. I2C
PSC9131RDB Reference Manual, Rev. C
Freescale Semiconductor 4-13
4.6 I2C
The PSC9131RDB use PSC9131 I2C1 bus, the table bellow describe the part used its address for read &
write its part number its relating control use and its company. the I2C circuit also consist of a 3pin header
for plug in to remote the IO Expander devices for Reset Configuration Word. by plugging to this 3pin J32
writing init value to the IO Expander and then write to the HRESET_REQ register this writing is auto-
maticaly turn the board OFF and ON this action perform a board power on sequence, which also drive
HRESET to low to load the reset configuration word.
Table 4-6. I2C Devices & Adresses
PART
NUMBER
COMPANY ADDRESS RELATED to Note
M24C02
ST
Microelectronics
0x52
DDR SPDRead 0xA4
Write 0xA5
0x53
RF
Connector1
See RF Board for more
information
Read 0xA7
Write 0xA6
0x51
RF
Connector2
See RF Board for more
information
Read 0xA3
Write 0xA2
LEA-6T-0 u-blox AG
0x42
GPSRead 0x83
Write 0x84
AT24C512B-T
H25-B
ATMEL
0x50
Boot SquenceRead 0xA1
Write 0xA0
ADT7461 Analog Device
0x4C
Thermal
Monitor
Read 0x99
Write 0x98
PCA9555PW PHILIPS
0x21
IO
EXPANDER
RCW
For remote Reset
Configuration word
Read 0x43
Write 0x42
PCA9555PW PHILIPS
0x23
IO
EXPANDER
RCW
For remote Reset
Configuration word
Read 0x47
Write 0x46
PCA9555PW PHILIPS
0x27
IO
EXPANDER
RCW
For remote Reset
Configuration word
Read 0x4F
Write 0x4E

14. PSC9131RDB Reference Manual, Rev. C
4-14 Freescale Semiconductor
Functional Description
Figure 4-9. PSC9131RDB I2C Block diagram
4.7 uSIM Interface
PSC9131 support a USIM interface. USIM is designed to facilitate communication to SIM cards.
PSC9131 provide one SIM card interface. Mode of operation supported is
Internal one wire interface: In this mode, only TX pin is used to connect the SIM card
PSC9131RDB support CLASS B & C SIM cards. Based on the BVDD voltage settings, SIM_VSEL J20
select the VCC mode if open 3.3V selected if close 1.8v selected.
Figure 4-10. uSIM Block diagram
PSC9131
I2C0
RF card2
Addr 0x53
Analog DeviceRF card1
U26U119J6 J9
Read 0xA7
Write0xA6
Addr 0x53
Read 0xA7
Write0xA6
LEA-6T-0
u-blox AGAddr 0x42
Read 0x85
Write0x84
U53
AT24C512B-T
ATMELAddr 0x50
Read 0xA1
Write0xA0GPS Module
H25-B
Boot Seq ADT7461
Thermal MonitorAddr 0x4C
Read 0x99
Write0x98
PHILIPS
U86
PCA9555PW
IOAddr 0x21
Read 0x43
Write0x42
EXPANDER RCW
PHILIPS
U60
PCA9555PW
IO
Addr 0x23
Read 0x47
Write0x46
EXPANDERRCW
PHILIPS
U67
PCA9555PW
IO
Addr 0x27
Read 0x4F
Write0x4E
EXPANDERRCW
3PINs External
Connector
J32
PSC9131
uSIM
Interface
UART1_CTS
1
2
3
J1
COP_SRTS
SIM_PD
SIM_LT_RST
SIM_LT_CLK
SIM_LT_TRXD
FMS006-0001
SIM
SOCKET
P1
YAMAICH
uSIM
Power
Translator
NCN4555
ON
Semiconductor
SIM_RST
SIM_CLK
SIM_TRXD
SIM_SVEN
VCC_MODE
J20
NO - 3.3V
NC - 1.8V
U59

15. TDM Interface (SLIC)
PSC9131RDB Reference Manual, Rev. C
Freescale Semiconductor 4-15
4.8 TDM Interface (SLIC)
PSC9131 support one TDM interface. Feature supported are
• Support for 256 channels
• Six wire interface
• 2-bit/4-bit/8-bit/16-bit word size support
• Shared data link mode, RX and TX share sync, clock and full duplex data
• Support for A-law/u-law is supported for 8-bit channels
• Configurable LSB or MSB first
In PSC9131RDB, TDM signals are connected to SLIC device for voice data transfer and also terminated
one RJ11 for telephone is mounted on the board (J26) The diagram below shows the TDM connection of
the PSC9131RDB. The slic device output its interapt to PSC9131 IFC_AD10 to get its interupt the user
should initiate this pin to its alternat GPIO option.
Figure 4-11. TDM SLIC Interface
4.9 GPS Module
The GPS Module use the LEA-6T-0 from u-blox is initiated via I2C bus 0 address ox42 (write 0x84 &
read 0x85) the data transfered to and from the GPS module is using the UART1 bus. inorder to be able to
use the GPS module the antana J31 should be connected. The TSEC_1588_TRIG in Canget its source
from the GPS Moduefor proper operation refer to ethernet 1588 clock block.
Figure 4-12. GPS Module Interface
PSC9131
TDM Interface ZARLINK
Le88266DLC
SLICSPI1&CS1
TDM_RXD
TDM_TXD
TDM_CLK
TDM_FRAME
HRESET_B
RJ11J26
PSC9131
GPS Interface
GPS ModuleI2C0 Addr 0x42
UART1_SIN
UART1_SOUT
GPS Antena
LEA-6T-0
u-blox AG
Read 0x85
Write0x84
J31
U119
GPS_10MHZ_CLK
GPS_1PPS_OUTPUT
CON1_XCVR_REF
CON2_XCVR_REF
J16
1
0
U43
100Mhz
Osc
66.66Mhz
Osc
Y3
Y4
SYS_CLK
TSEC_1588_TRIG_IN

16. PSC9131RDB Reference Manual, Rev. C
4-16 Freescale Semiconductor
Functional Description
4.10 PSC9131RDB USB
The PSC9131 has one USB 2.0 port that uses the ULPI mode to connect to external USB PHYs, the used
phy is USB3315 from SMSC. The controller may be independently configured for host or device modes.
To allow maximum flexibility for configuration, the PSC9131 multiplexes the USB port pins with either
LVDD-powered TSEC2 PHY signals or various CVDD-powered signals such as UART2, I2C1, GPIOs,
etc. the RDB used UART2 I2C1 & GPIOs muxed pins for USB ULPI function used CVDD power.
PSC9131RDB USB Block diagram
PSC9131
USB_D[0:7]
nHRESET
USB_ID
USB_STP
USB_CLK_PHY
USB_DIR
USB_CLK_R
USB_NXT
24Mhz
Osc
Y2
USB_VBUS_EN_B
VCC_5V VCC_USB_VBUS
MIC2075
MICREL
FAULT
D12
VCC_USB_VBUS
USB3315
SMSC
VBUS
D+
D-
D12
BUS2 OTG
J27
U48