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p4 over odp
solution, results
and comparison to a different approach
Gergely Pongrácz
Ericsson Research
Linaro Connect 2017, Budapest | © Ericsson Research 2017 | 2017-03-08 | Page 2
Performancevs. Flexibility
Inspired by Vinod Khosla @ ONS2014
Time
Technology
Evolution
Optimize for performance
today
Optimize for
flexibility
Inflection
point
These are the main drivers for SDN and NFV
meaning
- more flexibility
- easier and centralized control
- (close to) generic, programmable hardware
but we don’t want to entirely sacrifice performance
in this process!
Linaro Connect 2017, Budapest | © Ericsson Research 2017 | 2017-03-08 | Page 3
the rolefor p4 andodp
› Domain Specific Languages
(e.g. P4)
–intentionally limited language
› easier for “average” developers
› better overall performance
› less “generic” errors (e.g. memory
mgmt, locks)
› better for hardware vendors
–good tradeoff between high
performance and flexibility
› Open Data Plane (ODP)
–main goal is portability
–defines “good enough” abstraction
for most networking tasks
–implementation quality depends on
vendor support
› functionality
› packet handling performance
› scalability, etc.
Linaro Connect 2017, Budapest | © Ericsson Research 2017 | 2017-03-08 | Page 4
the p4/odp(macsad*)architecture
*MACSAD = Multi-Architecture Compiler System for Abstract Dataplanes
Linaro Connect 2017, Budapest | © Ericsson Research 2017 | 2017-03-08 | Page 5
Multi-targetCompiler(ELTE)
1. Hardware-independent „Core”
– P4 HLIR is used to generate the Intermediate Representation (IR)
– Our core compiler compiles the IR to a hardware independent C code with HAL API calls
2. Hardware-dependent „HAL”
– Implementing a well defined API that fulfills the requirements of most hardwares
– A static and thin library implementing networking primitives for a given target
– Written by a hardware expert
3. Switch program
– Compiled from the hardware-independent C code of the „Core” and the target-specific HAL
– Resulting in a hardware dependent switch program
P4 program
P4
HLIR
Intermediate
Representation
C compiler &
linker
„Core” code using
HAL API calls
HAL implementation for a
given target
Switch
program
Core
compiler
Linaro Connect 2017, Budapest | © Ericsson Research 2017 | 2017-03-08 | Page 6
Evaluationsetup
TrafficGenerator and P4Switch nodes
– Intel XEON E5-2630 6 cores, 12 threads, @ 2.3GHz, 2x8 GB DDR3 SDRAM
– Dual 10 Gbps NIC (Intel 82599ES)
– NFPA tool for automated tests with PktGen
2 x 10 Gbps
test traffic
(29.76 Mpps)
1 x 10 Gbps
test traffic
(14.88 Mpps)
Evaluation scenarios
Linaro Connect 2017, Budapest | © Ericsson Research 2017 | 2017-03-08 | Page 7
L2 forwarding
› Two lookup
tables
– SMAC & DMAC
– Exact maches
only
› Generating
digests
– For unseen
SMACs
› Demo controller
fills tables SMAC
and DMAC
according to the
digest received
1 x 10
Gbps TX
rate
64 128 256 512 1024 1280 1514
0
2000
4000
6000
8000
10000
12000
Fwdrate(Mbps) P4/DPDK
P4/ODP/socket
P4/ODP/DPDK
Linaro Connect 2017, Budapest | © Ericsson Research 2017 | 2017-03-08 | Page 8
L3 routing
› Simple L3
example
› Three lookup
tables
– IPv4_lpm,
nexthops,
send_frame
– LPM and exact
matches
› Demo controller
fills tables in
advance
1 x 10
Gbps TX
rate
64 128 256 512 1024 1280 1514
0
2000
4000
6000
8000
10000
12000
Fwdrate(Mbps) P4/DPDK
P4/ODP/socket
P4/ODP/DPDK
Linaro Connect 2017, Budapest | © Ericsson Research 2017 | 2017-03-08 | Page 9
some moreresults
› P4/DPDK has a Freescale LS2085 (ARM) variant
– good L2 performance: ~2.5 Mpps per core, ~18 Mpps per board
– other use cases are under test
› P4/DPDK scales well until hitting interface limit
› P4/ODP has a BananaPi (ARM) variant
– not built for high-performance, but proves easy portability
› P4/ODP is compiled to Cavium ThunderX
– high-end ARM-based network processor with 48 cores and high-perf buses
– first results are coming soon
› P4/ODP has a Netmap based backend as well
– performance is almost identical to DPDK on x86
results from SigComm 2016 demo
Linaro Connect 2017, Budapest | © Ericsson Research 2017 | 2017-03-08 | Page 10
Summary andnext steps
› P4 pipelines can achieve line rate with 1 core and real-life packet size mix in simple
use cases (L2, L3)
› Direct P4/DPDK pipeline outperforms P4/ODP and is close to reference examples
(OpenFlow, DPDK examples)
– but there are some low hanging fruits for optimize the P4/ODP pipeline, e.g. zero-copy I/O
› ODP without DPDK is not suitable for high performance on x86
› Next steps
– define and implement more use cases with both backends: e.g. VxLAN, BNG, mobile gateway
– more performance debugging and optimizations on P4/ODP
– scalability tests and comparisons to P4/DPDK
– try non-x86 high-end hardware (Cavium ThunderX) to prove portability and check performance
– publish results to a high-end conference, e.g. IEEE HPSR
Linaro Connect 2017, Budapest | © Ericsson Research 2017 | 2017-03-08 | Page 11
p4 projectmembers
› Unicamp FEEC (P4/ODP)
–Christian E. Rothenberg
–Gyanesh Patra
–Juan S. Mejia
–Fabricio R. Cesen
–Javier R. Q. Ancieta
› Ericsson Research
–Gergely Pongrácz
–Zoltán Kiss
› ELTE (P4/DPDK)
–Software Lab
› Máté Tejfel
› Dániel Horpácsi
› Dániel Leskó
› Róbert Kitlei
–CNL
› Sándor Laki
› Péter Vörös
Linaro Connect 2017, Budapest | © Ericsson Research 2017 | 2017-03-08 | Page 12
references
› P. G. Patra, C. E. Rothenberg, and G. Pongrácz, “MACSAD: MultiArchitecture
Compiler System for Abstract Dataplanes (Aka Partnering P4 with ODP),” in ACM
SIGCOMM’16 Demo and Poster Session, 2016.
› S. Laki, D. Horpácsi, P. Vörös, R. Kitlei, D. Leskó, and M. Tejfel, “High speed packet
forwarding compiled from protocol independent data plane specifications,” in ACM
SIGCOMM’16 Demo and Poster Session, 2016.
› L. Csikor et al, “NFPA: Network function performance analyzer,” in IEEE NFV-SDN,
2015.
› GIT links:
– P4/DPDK: https://github.com/P4ELTE/t4p4s
– P4/ODP: https://github.com/intrig-unicamp/mac
thankyou!
questions, comments?

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  • 1. p4 over odp solution, results and comparison to a different approach Gergely Pongrácz Ericsson Research
  • 2. Linaro Connect 2017, Budapest | © Ericsson Research 2017 | 2017-03-08 | Page 2 Performancevs. Flexibility Inspired by Vinod Khosla @ ONS2014 Time Technology Evolution Optimize for performance today Optimize for flexibility Inflection point These are the main drivers for SDN and NFV meaning - more flexibility - easier and centralized control - (close to) generic, programmable hardware but we don’t want to entirely sacrifice performance in this process!
  • 3. Linaro Connect 2017, Budapest | © Ericsson Research 2017 | 2017-03-08 | Page 3 the rolefor p4 andodp › Domain Specific Languages (e.g. P4) –intentionally limited language › easier for “average” developers › better overall performance › less “generic” errors (e.g. memory mgmt, locks) › better for hardware vendors –good tradeoff between high performance and flexibility › Open Data Plane (ODP) –main goal is portability –defines “good enough” abstraction for most networking tasks –implementation quality depends on vendor support › functionality › packet handling performance › scalability, etc.
  • 4. Linaro Connect 2017, Budapest | © Ericsson Research 2017 | 2017-03-08 | Page 4 the p4/odp(macsad*)architecture *MACSAD = Multi-Architecture Compiler System for Abstract Dataplanes
  • 5. Linaro Connect 2017, Budapest | © Ericsson Research 2017 | 2017-03-08 | Page 5 Multi-targetCompiler(ELTE) 1. Hardware-independent „Core” – P4 HLIR is used to generate the Intermediate Representation (IR) – Our core compiler compiles the IR to a hardware independent C code with HAL API calls 2. Hardware-dependent „HAL” – Implementing a well defined API that fulfills the requirements of most hardwares – A static and thin library implementing networking primitives for a given target – Written by a hardware expert 3. Switch program – Compiled from the hardware-independent C code of the „Core” and the target-specific HAL – Resulting in a hardware dependent switch program P4 program P4 HLIR Intermediate Representation C compiler & linker „Core” code using HAL API calls HAL implementation for a given target Switch program Core compiler
  • 6. Linaro Connect 2017, Budapest | © Ericsson Research 2017 | 2017-03-08 | Page 6 Evaluationsetup TrafficGenerator and P4Switch nodes – Intel XEON E5-2630 6 cores, 12 threads, @ 2.3GHz, 2x8 GB DDR3 SDRAM – Dual 10 Gbps NIC (Intel 82599ES) – NFPA tool for automated tests with PktGen 2 x 10 Gbps test traffic (29.76 Mpps) 1 x 10 Gbps test traffic (14.88 Mpps) Evaluation scenarios
  • 7. Linaro Connect 2017, Budapest | © Ericsson Research 2017 | 2017-03-08 | Page 7 L2 forwarding › Two lookup tables – SMAC & DMAC – Exact maches only › Generating digests – For unseen SMACs › Demo controller fills tables SMAC and DMAC according to the digest received 1 x 10 Gbps TX rate 64 128 256 512 1024 1280 1514 0 2000 4000 6000 8000 10000 12000 Fwdrate(Mbps) P4/DPDK P4/ODP/socket P4/ODP/DPDK
  • 8. Linaro Connect 2017, Budapest | © Ericsson Research 2017 | 2017-03-08 | Page 8 L3 routing › Simple L3 example › Three lookup tables – IPv4_lpm, nexthops, send_frame – LPM and exact matches › Demo controller fills tables in advance 1 x 10 Gbps TX rate 64 128 256 512 1024 1280 1514 0 2000 4000 6000 8000 10000 12000 Fwdrate(Mbps) P4/DPDK P4/ODP/socket P4/ODP/DPDK
  • 9. Linaro Connect 2017, Budapest | © Ericsson Research 2017 | 2017-03-08 | Page 9 some moreresults › P4/DPDK has a Freescale LS2085 (ARM) variant – good L2 performance: ~2.5 Mpps per core, ~18 Mpps per board – other use cases are under test › P4/DPDK scales well until hitting interface limit › P4/ODP has a BananaPi (ARM) variant – not built for high-performance, but proves easy portability › P4/ODP is compiled to Cavium ThunderX – high-end ARM-based network processor with 48 cores and high-perf buses – first results are coming soon › P4/ODP has a Netmap based backend as well – performance is almost identical to DPDK on x86 results from SigComm 2016 demo
  • 10. Linaro Connect 2017, Budapest | © Ericsson Research 2017 | 2017-03-08 | Page 10 Summary andnext steps › P4 pipelines can achieve line rate with 1 core and real-life packet size mix in simple use cases (L2, L3) › Direct P4/DPDK pipeline outperforms P4/ODP and is close to reference examples (OpenFlow, DPDK examples) – but there are some low hanging fruits for optimize the P4/ODP pipeline, e.g. zero-copy I/O › ODP without DPDK is not suitable for high performance on x86 › Next steps – define and implement more use cases with both backends: e.g. VxLAN, BNG, mobile gateway – more performance debugging and optimizations on P4/ODP – scalability tests and comparisons to P4/DPDK – try non-x86 high-end hardware (Cavium ThunderX) to prove portability and check performance – publish results to a high-end conference, e.g. IEEE HPSR
  • 11. Linaro Connect 2017, Budapest | © Ericsson Research 2017 | 2017-03-08 | Page 11 p4 projectmembers › Unicamp FEEC (P4/ODP) –Christian E. Rothenberg –Gyanesh Patra –Juan S. Mejia –Fabricio R. Cesen –Javier R. Q. Ancieta › Ericsson Research –Gergely Pongrácz –Zoltán Kiss › ELTE (P4/DPDK) –Software Lab › Máté Tejfel › Dániel Horpácsi › Dániel Leskó › Róbert Kitlei –CNL › Sándor Laki › Péter Vörös
  • 12. Linaro Connect 2017, Budapest | © Ericsson Research 2017 | 2017-03-08 | Page 12 references › P. G. Patra, C. E. Rothenberg, and G. Pongrácz, “MACSAD: MultiArchitecture Compiler System for Abstract Dataplanes (Aka Partnering P4 with ODP),” in ACM SIGCOMM’16 Demo and Poster Session, 2016. › S. Laki, D. Horpácsi, P. Vörös, R. Kitlei, D. Leskó, and M. Tejfel, “High speed packet forwarding compiled from protocol independent data plane specifications,” in ACM SIGCOMM’16 Demo and Poster Session, 2016. › L. Csikor et al, “NFPA: Network function performance analyzer,” in IEEE NFV-SDN, 2015. › GIT links: – P4/DPDK: https://github.com/P4ELTE/t4p4s – P4/ODP: https://github.com/intrig-unicamp/mac

Editor's Notes

  1. 3/17/20172010-12-10