This document discusses considerations for next generation virtualization platforms. It notes that current platforms have limitations based on the number of logical processors reported in the BIOS. It suggests using emulation rather than relying on logical processor counts, and removing restrictions on the number of logical processors to improve performance. Specifically, it discusses using the open source Bochs emulator which can emulate multiple hardware threads on multi-core processors through threading, even if BIOS only reports a single logical processor. This would allow assigning more virtual processors to guest operating systems than currently allowed.
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Content of presentation:
Multi-core processors
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Alluxio Community Office Hours
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Speaker: Bin Fan, Alluxio
Check alluxio.io for more events.
Join the community conversations on Slack: alluxio.io/slack
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Content of presentation:
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Conclusion
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1. Consideration to next
generation virtualization
platform
Use emulation and not depend on number of logical processor
Ryoichi Kida (ryouichi.kida@gmail.com)
2. Table of Contents
● Hardware architecture now in use
● Performance of XEON Processor
● Requirement of Running Guest OS
● Example of Enterprise BIOS Development
● Number of logical processor limitations on virtualization
● Discard number of logical processor limitations
● For the next…
3. Hardware architecture now in use
● The present processor inherits the Nehalem architecture
and is accelerating processing by improvement of
connection of a core and an external bus.
● A processor will use the Nehalem architecture as a base
from now on, and the product which can operate at high
speed will come out in a market with low power
consumption more by the improvement of a semiconductor
manufacturing process.
● A processor becomes connectable between processors by
high-speed Buss by the function called R-BOX. When this
function is used effectively, the composition of the
following processor systems is attained.
4. Basic Architecture of Processor(1)
● From Intel E7 Processor Hardware Manual
● Please insert graph
5. Basic Architecture of Processor(2)
● From Intel E7 Processor Hardware Manual
● Please insert graph
6. Processor Topology
● processors is connected by the function called QPI
(Quick Path Interconnect). This Buss communicates the
message between processors at a high-speed. Bus's
performance serves as 6.4 GT/s. It can see as the
processor which exists in two or more sockets by the
original command of CPU, and one processor with the
big core.
7. Performance of XEON Processor
● The speed in a Westmere-Ex (E7) processor is
considered before the present SandyBridge.
● In fact, the computing speed of this processor is
128GFPS, and throughput is the same as the processor
of the supercomputer called a KEI(京).
● A processor very high-speed as a processor can be used
only by the number of processors differing from its
topology.
8. Requirement of Running Guest OS
● Requirements required to perform OS of 64 bits/32 bits of
Intel are preparing an ACPI table. A common standard is
shown in an ACPI table and the following items are included
in it.
● Table basic information
● The number of processors
● Memory allotment size to a processor
● I/O information
● Memory information
● Others
● For details, refer to the following homepages.
● http://www.acpi.info
10. Example of Enterprise BIOS
Development
● The example of development of BIOS for Enterprise Server.
● The information about the newest processor can be obtained from
Intel. Therefore, it can design based on the information.
● In the case of the newest processor, development of debugger has
not fulfilled demand in many cases. If it is original, debugger
called ITP will be connected, but it cannot respond to change of
the number of cores, or the architecture in many cases.In fact, an
emulator is prepared.
● The open source called bochs as an emulator is used
● http://bochs.sourceforge.net
● This open source can emulate the hardware of 32 bits/64 bits by
incorporating a hardware dependence portion in sources.
11. … on bochs source and archives
● The interesting thing is written if the sources of bochs is
read.
● In bochs, when a processor is SMP composition, it
processes by only the number of processors preparing a
thread.
● Since it is an emulation, it becomes late, but if the
throughput of the present XEON Processor is still
considered, this function has an interesting thing.
12. Number of logical processor
limitations on virtualization
● In the present virtualization, host OS can be used only
to the number of logic processors acquired from BIOS.
● A limit is among the numbers of logic processors
assigned to guest OS.
● By this system, there is no load of host OS so then, and
it is still generous rather.
● In order to do one's best more and to be given, the view
of removing restrictions of the number of logic
processors also exists.