Modeling examples

Prepared by Prof. Anand H. D., Dept. of ECE, Dr. AIT, Bengaluru-56
MODELING EXAMPLES
Mr. Anand H. D.
1
Modeling Examples
Department of Electronics & Communication Engineering
Dr. Ambedkar Institute of Technology
Bengaluru-56

Generic Shift Register State Machine Modeling Interacting State Machines
Modeling a Moore FSM Modeling a Mealy FSM
Prepared by Prof. Anand H. D., Dept. of ECE, Dr. AIT, Bengaluru-56 2
Modeling Examples
SYLLABUS:
Generic Shift Register
State Machine Modeling
Interacting State Machines
Modeling a Moore FSM
Modeling a Mealy FSM

Modeling Examples
Generic Shift Register
A Generic Serial-in, Serial-out Shift Register can be modeled using for-loop with an always statement.
The number of registers is specified as a parameter so that it can be modified when Generic Shift Register is
instantiated in other design.
module Shift_Reg (D, Clock, Z)
input D, Clock;
output Z;
parameter NUM_REG = 6;
reg [1: NUM_REG] Q;
integer P;
always @ (negedge CLOCK)
begin
for (P=1; P < NUM_REG ;P=P+1)
Q[P+1] = Q[P];
Q[1] = D;
end
assign Z= Q[NUM_REG];
endmodule
Shift registers of varying sizes can be obtained by instantiating module
Shift_Reg using different parameters.
Shift_Reg SRA (Data, Clk, Za)
Shift_Reg SRA #4 (Data, Clk, Zb)
Shift_Reg SRA #10 (Data, Clk, Zc)
module Dummy
wire Data, Clk, Za, Zb, Zc)
endmodule;
1 2 3 4 5 6
Q[1] Q[2] Q[3] Q[4] Q[5] Q[6]
Q[NUM_REG]
D
Z

Modeling Examples
Generic Shift Register State Machine Modeling
State machines can usually be modeled using a case statement in a process.
The state information is stored in a signal.
The multiple branches of the case statement contain the behavior for each
state.
Here is an example of a simple multiplication algorithm represented as a
state machine.
•When RESET signal is high, the accumulator ACC and the
counter COUNT are initialized.
•When RESET goes low, multiplication starts.
•If the bit of the multiplier MPLR in position COUNT is 1', the multiplicand
MCND is added to the accumulator.
•Next, the multiplicand is left-shifted by one bit and the counter is
incremented.
•If COUNT is 16, multiplication is complete and the DONE signal is set high.
•If not, the COUNT bit of the multiplier MPLR is checked and the process
repeated.
ADD
SHIFT
INIT
Reset ==0
Count ==16
Reset ==1
Reset ACC
Initialize COUNT
If MPLR[COUNT]
is 1 then ADD
MCND to ADD
Increment COUNT
Left Shift MCND
State Diagram for Multiplier

Modeling Examples
module Multiply (MPLR, MCND, Clock, Reset, DONE, ACC);
input [15:0] MPLR, MCND);
input Clock, Reset;
output DONE;
reg DONE;
output [31:0] ACC;
reg ACC;
parameter INIT = 0; ADD = 1; SHIFT = 2;
reg [0:1] Mpy_State;
reg [0:1] Mcnd_State;
//MPLR is multiplier and MCND is multiplicand
initial Mpy_State = INIT; //initial State is INIT
always @ (negedge Clock) begin: Process
integer COUNT;
case (Mpy_State)
reg DONE;
INIT:
if (Reset)
Mpy_State = INIT;
else
begin
ACC = 0;
COUNT = 0;
Mpy_State = ADD;
DONE= 0;
ADD
SHIFT
Reset ==0
Count ==16
Reset ==1
Reset ACC
Initialize COUNT
If MPLR[COUNT] is 1 then
ADD MCND to ADD
Increment COUNT
Left Shift MCND
INIT

Modeling Examples
Mcnd_Temp [15:0] = MCND;
Mcnd_Temp [31:16] = 16’d0;
end
ADD:
begin
if (MPLR[COUNT])
ACC = ACC + Mcnd_Temp;
Mpy_State = SHIFT;
end
SHIFT:
begin
Mcnd_Temp = {Mcnd_Temp [30:0], 1’b0};
COUNT = COUNT + 1;
if ( COUNT = = 16)
begin
Mpy_State = INIT;
DONE=1;
end
else
Mpy_State = ADD:
end
endcase
end
endmodule
ADD
SHIFT
Reset ==0
Count ==16
Reset ==1
Reset ACC
Initialize COUNT
ADD MCND to ADD
Increment COUNT
Left Shift MCND
INIT

Modeling Examples
The register Mpy_State holds the state of the model
Initially, the model is in state INIT and it stays in this state as long
as RESET is true.
When RESET is false, the accumulator ACC is cleared, the counter
COUNT is reset, the multiplicand MCND is loaded into temporary
variable Mcnd_Temp, and the model advances to state ADD.
When the model is in ADD state, the multiplicand, Mcnd_Temp is
added ACC only if the bit at the COUNT position of the multipler is
a 1 and then the model advances to state SHIFT.
In SHIFT state the multiplier is shifted left once, the counter is
incremented and
if the counter value is 16, DONE is set to true and model returns to
INIT state.
At this time ACC contains the result of multiplication.
If the counter value is less than 16, the model repeats itself going
through states ADD and SHIFT until the counter value becomes 16.
State transitions occurs at every negative edge of the clock; this is
specified by timing control @(negedge Clock)
ADD
SHIFT
Reset ==0
Count ==16
Reset ==1
Reset ACC
Initialize COUNT
ADD MCND to ADD
Increment COUNT
Left Shift MCND
INIT

Modeling Examples
Interacting state machines can be described as separate
processes communicating via common signals.
Consider the state transition diagram shown in Figure for
two interacting processes, TX, a transmitter, and MP, a
microprocessor.
If process TX is not busy, process MP sets the data to be
transmitted on a data bus and sends a
signal, LOAD_TX, to process TX to load the data and to
begin transmitting.
A signal, TX_BUSY, is set by process TX during
transmission to indicate that it is busy and that it cannot
receive any further data from process MP
A skeleton model for these two interacting processes is
shown in next. Only the control signals and state
transitions are shown. Data manipulation code is not
described.
M1 M2
M3
(TX_Busy==1)
Load_TX==0
(TX_Busy==0)
Load_TX==1
PROCESS MP
T4 T1
T2
(Load_TX==0)
(TX_Busy==1)
TX_Busy==0
PROCESS TX
T3
Note : Expressions in Parentheses indicate control

Modeling Examples
module Intersecting_FSM (Clock);
input Clock;
parameter M1=0, M2=1, M3=2;
parameter T1=0, T2=1, T3=2 , T4=3;
reg [0:1] MP_State;
reg [0:1] TX_State;
reg Load_TX, TX_Busy;
Note : Expressions in Parentheses
indicate control
always @(negedge Clock) begin MP
case (MP_State)
M1:
begin
Load_TX=1;
MP_State = M2;
end
M2:
if (TX_Busy)
begin
MP_State = M3;
Load_Tx=0
end
M1 M2
M3
(TX_Busy==1)
Load_TX==0
(TX_Busy==0)
Load_TX==1
PROCESS MP
T4 T1
T2
(Load_TX==0)
(TX_Busy==1)
TX_Busy==0
PROCESS TX
T3

Modeling Examples
Note : Expressions in Parentheses
indicate control
M3:
if (~TX_Busy)
MP_State = M1;
endcase
end
always @(negedge Clock) begin TX
case (TX_State)
T1:
if (Load_TX);
begin
TX_State = T2;
TX_Busy = 1;
end
T2:
TX_State = T3;
T3:
TX_State = T4;
T4:
begin
TX_Busy=0;
TX_State = T4;
end
endcase
end
endmodule
T4 T1
T2
(Load_TX==0)
(TX_Busy==1)
TX_Busy==0
PROCESS TX
T3
M1 M2
M3
(TX_Busy==1)
Load_TX==0
(TX_Busy==0)
Load_TX==1
PROCESS MP

Modeling Examples
Sequence of actions for the 2 Interacting Processes

Modeling Examples
module Intersecting_FSM 2(Clock);
input Clock;
parameter D1=0, D2=1, D3=2;
parameter R1=0, R2=1;
reg [0:1] Div_State;
reg [0:1] RX_State;
reg New_Clock;
D1
D2D3
New_Clock==0New_Clock==1
PROCESS DIV
always @(posedge Clock) begin DIV
case (Div_State)
D1:
begin
Div_State = D2;
New_clock=0;
end
D2:
Div_State = D3;
R1
PROCESS RX
R2
Consider another example of 2 interacting processes, DIV, a clock-divider and RX, a receiver.
In this case the DIV generates a new clock, New_Clock and RX goes through its sequence of states of
synchronized to this new clock.

Modeling Examples
D3:
begin
New_clock = 1;
Div_State = D1;
end
endcase
end
always @(negdge New_Clock) begin RX
case (RX_State)
RX_State = R2;
RX_State = R1;
end
endcase
endmodule
Sequential block DIV generates a new clock New_Clock as it goes through its
sequence of states.
The state transitions in this process occur on the rising edge of Clock.
Sequential block RX is executed every time when falling edge of the
New_Clock occurs.
D1
D2D3
New_Clock==0New_Clock==1
PROCESS DIV
R1
PROCESS RX
R2

Modeling Examples
Interaction between the Processes RX and DIV

Modeling Examples
ST1 ST3
ST2
(A==1)
ST0
(A==0)
(A==0)
(A==0)
(A==0) (A==1)
(A==1)
Z=1
Z=1Z=0
Z=0
(A==1)
State Diagram of a Moore machine
The output of a Moore Finite State Machine (FSM) depends only on the state and not on its inputs.
This type of behavior can be modeled using an always statement with a case statement that switches on the state value,
module Moore_FSM(A, Clock, Z);
input A, Clock;
output Z;
reg Z;
parameter ST0=0, ST1=1, ST2=2, ST3=3;
reg [0:1] Moore_State;
always @ (negedge Clock)
case (Moore_State)
ST0:
begin
Z=1;
if (A)
Moore_State = ST2;
end
ST1:
begin
Z=0;
if (A)
Moore_State = ST3;
end

Modeling Examples
ST1 ST3
ST2
(A==1)
ST0
(A==0)
(A==0)
(A==0)
(A==0) (A==1)
(A==1)
Z=1
Z=1Z=0
Z=0
(A==1)
State Diagram of a Moore machine
ST2:
begin
Z=0;
if (~A)
Moore_State = ST1;
else
Moore_State = ST3;
end
ST3:
begin
Z=1;
if (A)
Moore_State = ST0;
end
endcase
endmodule

Modeling Examples
In a Mealy Finite State Machine (FSM) , the outputs not only depend on the state of the machine but also on its inputs.
This type of FSM can be modeled in similar way as that of the Moore FSM, that is using a single always statement.
To show variety of language, a different style is used to model Mealy machine. In this case 2 always statements, one
that models synchronous aspect of FSM and other models the combinational part of FSM.
State Transition Table of a Mealy machine
module Mealy_FSM(A, Clock, Z);
input A, Clock;
output Z;
reg Z;
parameter ST0=0, ST1=1, ST2=2, ST3=3;
reg [1:2] P_State, N_State;
always @ (negedge Clock)
P_State = N_State;
always @ (P_State or A) begin: COMB_PART
case (P_State)
ST0:
if (A)
begin
Z=1;
N_State = ST3;
end

Modeling Examples
ST1:
if (A)
begin
Z=0;
N_State = ST0;
end
else
Z=1;
else
Z=0;
ST2:
if (~A)
Z=0;
else
begin
Z=1;
N_State = ST1;
end

Modeling Examples
ST3:
begin
Z=0;
if (~A)
N_State = ST2;
else
N_State = ST1;
end
endcase
end
endmodule
In a Mealy Finite State Machine (FSM) , it is important to put the signals in event list for
the combinational part sequential block since the outputs may be directly depend on the
inputs independent of clock.
Such a condition not occur in a Moore FSM since outputs depends only on states and state
changes occur synchronously on cock.

Modeling Examples
Reference
J. Bhasker,” A verilog HDL Primer” BS
Publications , 2nd Edition.

Modeling examples

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