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Mips opcodes
- 1. MIPS Instruction Types Type R I J -31format (bits) -0opcode (6) rs (5) rt (5) rd (5) shamt (5) funct (6) opcode (6) rs (5) rt (5) immediate (16) opcode (6) address (26) I-Type Instructions (All opcodes except 000000, 00001x, and 0100xx) I-type instructions have a 16-bit immediate field that codes an immediate operand, a branch target offset, or a displacement for a memory operand. For a branch target offset, the immediate field contains the signed difference between the address of the following instruction and the R-Type Instructions (Opcode 000000) target label, with the two low order bits dropped. The Main processor instructions that do not require a target dropped bits are always 0 since instructions are wordaddress, immediate value, or branch displacement use an aligned. R-type coding format. This format has fields for specify- For the bgez, bgtz, blez, and bltz instructions, the ing of up to three registers and a shift amount. rt field is used as an extension of the opcode field. For instructions that do not use all of these fields, the unrt used fields are coded with all 0 bits. All R-type instruc- opcode rs (6) (5) (5) tions use a 000000 opcode. The operation is specified by Instruction the function field. addi rt, rs, immediate opcode rs rt rd sa function addiu rt, rs, immediate (6) (5) (5) (5) (5) (6) andi rt, rs, immediate Instruction Function beq rs, rt, label add rd, rs, rt 100000 bgez rs, label addu rd, rs, rt 100001 bgtz rs, label and rd, rs, rt 100100 blez rs, label break 001101 bltz rs, label div rs, rt 011010 bne rs, rt, label divu rs, rt 011011 lb rt, immediate(rs) jalr rd, rs 001001 lbu rt, immediate(rs) jr rs 001000 lh rt, immediate(rs) mfhi rd 010000 lhu rt, immediate(rs) mflo rd 010010 lui rt, immediate mthi rs 010001 lw rt, immediate(rs) mtlo rs 010011 lwc1 rt, immediate(rs) mult rs, rt 011000 ori rt, rs, immediate multu rs, rt 011001 sb rt, immediate(rs) nor rd, rs, rt 100111 slti rt, rs, immediate or rd, rs, rt 100101 sltiu rt, rs, immediate sll rd, rt, sa 000000 sh rt, immediate(rs) sllv rd, rt, rs 000100 sw rt, immediate(rs) slt rd, rs, rt 101010 swc1 rt, immediate(rs) sltu rd, rs, rt 101011 xori rt, rs, immediate sra rd, rt, sa 000011 srav srl srlv sub subu syscall xor rd, rt, rs rd, rt, sa rd, rt, rs rd, rs, rt rd, rs, rt 000111 000010 000110 100010 100011 001100 rd, rs, rt 100110 immediate (16) Opcode Notes 001000 001001 001100 000100 000001 rt = 00001 000111 rt = 00000 000110 rt = 00000 000001 rt = 00000 000101 100000 100100 100001 100101 001111 100011 110001 001101 101000 001010 001011 101001 101011 111001 001110
- 2. J-Type Instructions (Opcode 00001x) OPCODE map The only J-type instructions are the jump instructions j Table of opcodes for all instructions: and jal. These intructions require a 26-bit coded address 000 001 010 011 100 101 110 111 field to specify the target of the jump. The coded address is formed from the bits at positions 27 to 2 in the binary 000 R-type j jal beq bne blez bgtz representation of the address. The bits at positions 1 and 0 001 addi addiu slti sltiu andi ori xori are always 0 since instructions are word-aligned. 010 When a J-type instruction is executed, a full 32-bit jump lhi trap target address is formed by concatenating the high order 011 llo four bits of the PC (the address of the instruction 100 lb lh lw lbu lhu following the jump), the 26 bits of the target field, and 101 sb sh sw two 0 bits. 110 opcode target 111 (6) (26) Instruction Opcode Target FUNC map of R-type instructions j label 000010 coded address of label Table of function codes for register-format instructions: jal label 000011 coded address of label 000 001 010 011 100 101 110 111 Coprocessor Instructions (Opcode 0100xx) The only instructions that are described here are the floating point instructions that are common to all processors in the MIPS family. All coprocessor instructions instructions use opcode 0100xx. The last two bits specify the coprocessor number. Thus all floating point instructions use opcode 010001. 000 sll 001 jr srl sra sllv srlv srav xor nor jalr 010 mfhi mthi mflo mtlo 011 mult multu div divu 100 add subu and addu sub or slt sltu The instruction is broken up into fields of the same sizes 101 as in the R-type instruction format. However, the fields 110 are used in different ways. 111 Most floating point intructions use the format field to specify a numerical coding format: single precision (.s), douSome R-type instructions grouped by their familiarity: ble precision (.d), or fixed point (.w). The mfc1 and Function mtc1 instructions uses the format field as an extension of Instruction add rd, rs, rt 100000 the function field. opcode format (6) (5) Instruction add.s fd, fs, ft cvt.s.w fd, fs, ft cvt.w.s fd, fs, ft div.s fd, fs, ft mfc1 ft, fs mov.s fd, fs mtc1 ft, fs mul.s fd, fs, ft sub.s fd, fs, ft ft (5) Function 000000 100000 100100 000011 000000 000110 000000 000010 000001 fs (5) Format 10000 10100 10000 10000 00000 10000 00100 10000 10000 fd (5) function (6) addu sub subu rd, rs, rt rd, rs, rt rd, rs, rt 100001 100010 100011 and or xor nor rd, rs, rt rd, rs, rt rd, rs, rt rd, rs, rt 100100 100101 100110 100111 slt sltu rd, rs, rt rd, rs, rt 101010 101011 sll srl sllv srlv sra srav rd, rt, sa rd, rt, sa rd, rt, rs rd, rt, rs rd, rt, sa rd, rt, rs 000000 000010 000100 000110 000011 000111