ARM (Advance RISC Machine) is one of the most licensed and thus widespread processor cores in the world.Used especially in portable devices due to low power consumption and reasonable performance.Several interesting extension available like THUMB instruction set and Jazelle Java Machine.
ARM (Advance RISC Machine) is one of the most licensed and thus widespread processor cores in the world.Used especially in portable devices due to low power consumption and reasonable performance.Several interesting extension available like THUMB instruction set and Jazelle Java Machine.
NUMERICAL SIMULATIONS OF HEAT AND MASS TRANSFER IN CONDENSING HEAT EXCHANGERS...ssuser7dcef0
Power plants release a large amount of water vapor into the
atmosphere through the stack. The flue gas can be a potential
source for obtaining much needed cooling water for a power
plant. If a power plant could recover and reuse a portion of this
moisture, it could reduce its total cooling water intake
requirement. One of the most practical way to recover water
from flue gas is to use a condensing heat exchanger. The power
plant could also recover latent heat due to condensation as well
as sensible heat due to lowering the flue gas exit temperature.
Additionally, harmful acids released from the stack can be
reduced in a condensing heat exchanger by acid condensation. reduced in a condensing heat exchanger by acid condensation.
Condensation of vapors in flue gas is a complicated
phenomenon since heat and mass transfer of water vapor and
various acids simultaneously occur in the presence of noncondensable
gases such as nitrogen and oxygen. Design of a
condenser depends on the knowledge and understanding of the
heat and mass transfer processes. A computer program for
numerical simulations of water (H2O) and sulfuric acid (H2SO4)
condensation in a flue gas condensing heat exchanger was
developed using MATLAB. Governing equations based on
mass and energy balances for the system were derived to
predict variables such as flue gas exit temperature, cooling
water outlet temperature, mole fraction and condensation rates
of water and sulfuric acid vapors. The equations were solved
using an iterative solution technique with calculations of heat
and mass transfer coefficients and physical properties.
HEAP SORT ILLUSTRATED WITH HEAPIFY, BUILD HEAP FOR DYNAMIC ARRAYS.
Heap sort is a comparison-based sorting technique based on Binary Heap data structure. It is similar to the selection sort where we first find the minimum element and place the minimum element at the beginning. Repeat the same process for the remaining elements.
Sachpazis:Terzaghi Bearing Capacity Estimation in simple terms with Calculati...Dr.Costas Sachpazis
Terzaghi's soil bearing capacity theory, developed by Karl Terzaghi, is a fundamental principle in geotechnical engineering used to determine the bearing capacity of shallow foundations. This theory provides a method to calculate the ultimate bearing capacity of soil, which is the maximum load per unit area that the soil can support without undergoing shear failure. The Calculation HTML Code included.
About
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
• Remote control: Parallel or serial interface.
• Compatible with MAFI CCR system.
• Compatible with IDM8000 CCR.
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
• Easy in configuration using DIP switches.
Technical Specifications
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
Key Features
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
• Remote control: Parallel or serial interface
• Compatible with MAFI CCR system
• Copatiable with IDM8000 CCR
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
Application
• Remote control: Parallel or serial interface.
• Compatible with MAFI CCR system.
• Compatible with IDM8000 CCR.
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
• Easy in configuration using DIP switches.
Hierarchical Digital Twin of a Naval Power SystemKerry Sado
A hierarchical digital twin of a Naval DC power system has been developed and experimentally verified. Similar to other state-of-the-art digital twins, this technology creates a digital replica of the physical system executed in real-time or faster, which can modify hardware controls. However, its advantage stems from distributing computational efforts by utilizing a hierarchical structure composed of lower-level digital twin blocks and a higher-level system digital twin. Each digital twin block is associated with a physical subsystem of the hardware and communicates with a singular system digital twin, which creates a system-level response. By extracting information from each level of the hierarchy, power system controls of the hardware were reconfigured autonomously. This hierarchical digital twin development offers several advantages over other digital twins, particularly in the field of naval power systems. The hierarchical structure allows for greater computational efficiency and scalability while the ability to autonomously reconfigure hardware controls offers increased flexibility and responsiveness. The hierarchical decomposition and models utilized were well aligned with the physical twin, as indicated by the maximum deviations between the developed digital twin hierarchy and the hardware.
Using recycled concrete aggregates (RCA) for pavements is crucial to achieving sustainability. Implementing RCA for new pavement can minimize carbon footprint, conserve natural resources, reduce harmful emissions, and lower life cycle costs. Compared to natural aggregate (NA), RCA pavement has fewer comprehensive studies and sustainability assessments.
6th International Conference on Machine Learning & Applications (CMLA 2024)ClaraZara1
6th International Conference on Machine Learning & Applications (CMLA 2024) will provide an excellent international forum for sharing knowledge and results in theory, methodology and applications of on Machine Learning & Applications.
Hybrid optimization of pumped hydro system and solar- Engr. Abdul-Azeez.pdffxintegritypublishin
Advancements in technology unveil a myriad of electrical and electronic breakthroughs geared towards efficiently harnessing limited resources to meet human energy demands. The optimization of hybrid solar PV panels and pumped hydro energy supply systems plays a pivotal role in utilizing natural resources effectively. This initiative not only benefits humanity but also fosters environmental sustainability. The study investigated the design optimization of these hybrid systems, focusing on understanding solar radiation patterns, identifying geographical influences on solar radiation, formulating a mathematical model for system optimization, and determining the optimal configuration of PV panels and pumped hydro storage. Through a comparative analysis approach and eight weeks of data collection, the study addressed key research questions related to solar radiation patterns and optimal system design. The findings highlighted regions with heightened solar radiation levels, showcasing substantial potential for power generation and emphasizing the system's efficiency. Optimizing system design significantly boosted power generation, promoted renewable energy utilization, and enhanced energy storage capacity. The study underscored the benefits of optimizing hybrid solar PV panels and pumped hydro energy supply systems for sustainable energy usage. Optimizing the design of solar PV panels and pumped hydro energy supply systems as examined across diverse climatic conditions in a developing country, not only enhances power generation but also improves the integration of renewable energy sources and boosts energy storage capacities, particularly beneficial for less economically prosperous regions. Additionally, the study provides valuable insights for advancing energy research in economically viable areas. Recommendations included conducting site-specific assessments, utilizing advanced modeling tools, implementing regular maintenance protocols, and enhancing communication among system components.
Welcome to WIPAC Monthly the magazine brought to you by the LinkedIn Group Water Industry Process Automation & Control.
In this month's edition, along with this month's industry news to celebrate the 13 years since the group was created we have articles including
A case study of the used of Advanced Process Control at the Wastewater Treatment works at Lleida in Spain
A look back on an article on smart wastewater networks in order to see how the industry has measured up in the interim around the adoption of Digital Transformation in the Water Industry.
Cosmetic shop management system project report.pdfKamal Acharya
Buying new cosmetic products is difficult. It can even be scary for those who have sensitive skin and are prone to skin trouble. The information needed to alleviate this problem is on the back of each product, but it's thought to interpret those ingredient lists unless you have a background in chemistry.
Instead of buying and hoping for the best, we can use data science to help us predict which products may be good fits for us. It includes various function programs to do the above mentioned tasks.
Data file handling has been effectively used in the program.
The automated cosmetic shop management system should deal with the automation of general workflow and administration process of the shop. The main processes of the system focus on customer's request where the system is able to search the most appropriate products and deliver it to the customers. It should help the employees to quickly identify the list of cosmetic product that have reached the minimum quantity and also keep a track of expired date for each cosmetic product. It should help the employees to find the rack number in which the product is placed.It is also Faster and more efficient way.
RAT: Retrieval Augmented Thoughts Elicit Context-Aware Reasoning in Long-Hori...
07-arm_overview.ppt
1. 1
TM
T H E A R C H I T E C T U R E F O R T H E D I G I T A L W O R L D
The ARM Architecture
2. 2
TM 2
39v10 The ARM Architecture
Agenda
Introduction to ARM Ltd
Programmers Model
Instruction Set
System Design
Development Tools
3. 3
TM 3
39v10 The ARM Architecture
ARM Ltd
Founded in November 1990
Spun out of Acorn Computers
Designs the ARM range of RISC processor
cores
Licenses ARM core designs to semiconductor
partners who fabricate and sell to their
customers.
ARM does not fabricate silicon itself
Also develop technologies to assist with the
design-in of the ARM architecture
Software tools, boards, debug hardware,
application software, bus architectures,
peripherals etc
6. 6
TM 6
39v10 The ARM Architecture
ARM provides hard and soft views to licencees
RTL and synthesis flows
GDSII layout
Licencees have the right to use hard or soft views of the IP
soft views include gate level netlists
hard views are DSMs
OEMs must use hard views
to protect ARM IP
Intellectual Property
7. 7
TM 7
39v10 The ARM Architecture
Agenda
Introduction to ARM Ltd
Programmers Model
Instruction Sets
System Design
Development Tools
8. 8
TM 8
39v10 The ARM Architecture
Data Sizes and Instruction Sets
The ARM is a 32-bit architecture.
When used in relation to the ARM:
Byte means 8 bits
Halfword means 16 bits (two bytes)
Word means 32 bits (four bytes)
Most ARM’s implement two instruction sets
32-bit ARM Instruction Set
16-bit Thumb Instruction Set
Jazelle cores can also execute Java bytecode
9. 9
TM 9
39v10 The ARM Architecture
Processor Modes
The ARM has seven basic operating modes:
User : unprivileged mode under which most tasks run
FIQ : entered when a high priority (fast) interrupt is raised
IRQ : entered when a low priority (normal) interrupt is raised
Supervisor : entered on reset and when a Software Interrupt
instruction is executed
Abort : used to handle memory access violations
Undef : used to handle undefined instructions
System : privileged mode using the same registers as user mode
10. 11
TM 11
39v10 The ARM Architecture
Register Organization Summary
User
mode
r0-r7,
r15,
and
cpsr
r8
r9
r10
r11
r12
r13 (sp)
r14 (lr)
spsr
FIQ
r8
r9
r10
r11
r12
r13 (sp)
r14 (lr)
r15 (pc)
cpsr
r0
r1
r2
r3
r4
r5
r6
r7
User
r13 (sp)
r14 (lr)
spsr
IRQ
User
mode
r0-r12,
r15,
and
cpsr
r13 (sp)
r14 (lr)
spsr
Undef
User
mode
r0-r12,
r15,
and
cpsr
r13 (sp)
r14 (lr)
spsr
SVC
User
mode
r0-r12,
r15,
and
cpsr
r13 (sp)
r14 (lr)
spsr
Abort
User
mode
r0-r12,
r15,
and
cpsr
Thumb state
Low registers
Thumb state
High registers
Note: System mode uses the User mode register set
11. 12
TM 12
39v10 The ARM Architecture
The Registers
ARM has 37 registers all of which are 32-bits long.
1 dedicated program counter
1 dedicated current program status register
5 dedicated saved program status registers
30 general purpose registers
The current processor mode governs which of several banks is
accessible. Each mode can access
a particular set of r0-r12 registers
a particular r13 (the stack pointer, sp) and r14 (the link register, lr)
the program counter, r15 (pc)
the current program status register, cpsr
Privileged modes (except System) can also access
a particular spsr (saved program status register)
12. 13
TM 13
39v10 The ARM Architecture
Program Status Registers
Condition code flags
N = Negative result from ALU
Z = Zero result from ALU
C = ALU operation Carried out
V = ALU operation oVerflowed
Sticky Overflow flag - Q flag
Architecture 5TE/J only
Indicates if saturation has occurred
J bit
Architecture 5TEJ only
J = 1: Processor in Jazelle state
Interrupt Disable bits.
I = 1: Disables the IRQ.
F = 1: Disables the FIQ.
T Bit
Architecture xT only
T = 0: Processor in ARM state
T = 1: Processor in Thumb state
Mode bits
Specify the processor mode
27
31
N Z C V Q
28 6
7
I F T mode
16
23 8
15 5 4 0
24
f s x c
U n d e f i n e d
J
13. 14
TM 14
39v10 The ARM Architecture
When the processor is executing in ARM state:
All instructions are 32 bits wide
All instructions must be word aligned
Therefore the pc value is stored in bits [31:2] with bits [1:0] undefined (as
instruction cannot be halfword or byte aligned).
When the processor is executing in Thumb state:
All instructions are 16 bits wide
All instructions must be halfword aligned
Therefore the pc value is stored in bits [31:1] with bit [0] undefined (as
instruction cannot be byte aligned).
When the processor is executing in Jazelle state:
All instructions are 8 bits wide
Processor performs a word access to read 4 instructions at once
Program Counter (r15)
14. 15
TM 15
39v10 The ARM Architecture
Vector Table
Exception Handling
When an exception occurs, the ARM:
Copies CPSR into SPSR_<mode>
Sets appropriate CPSR bits
Change to ARM state
Change to exception mode
Disable interrupts (if appropriate)
Stores the return address in LR_<mode>
Sets PC to vector address
To return, exception handler needs to:
Restore CPSR from SPSR_<mode>
Restore PC from LR_<mode>
This can only be done in ARM state.
Vector table can be at
0xFFFF0000 on ARM720T
and on ARM9/10 family devices
FIQ
IRQ
(Reserved)
Data Abort
Prefetch Abort
Software Interrupt
Undefined Instruction
Reset
0x1C
0x18
0x14
0x10
0x0C
0x08
0x04
0x00
15. 16
TM 16
39v10 The ARM Architecture
Development of the
ARM Architecture
SA-110
ARM7TDMI
4T
1
Halfword
and signed
halfword /
byte support
System
mode
Thumb
instruction
set
2
4
ARM9TDMI
SA-1110
ARM720T ARM940T
Improved
ARM/Thumb
Interworking
CLZ
5TE
Saturated maths
DSP multiply-
accumulate
instructions
XScale
ARM1020E
ARM9E-S
ARM966E-S
3
Early ARM
architectures
ARM9EJ-S
5TEJ
ARM7EJ-S
ARM926EJ-S
Jazelle
Java bytecode
execution
6
ARM1136EJ-S
ARM1026EJ-S
SIMD Instructions
Multi-processing
V6 Memory
architecture (VMSA)
Unaligned data
support
16. 17
TM 17
39v10 The ARM Architecture
Agenda
Introduction to ARM Ltd
Programmers Model
Instruction Sets
System Design
Development Tools
17. 18
TM 18
39v10 The ARM Architecture
ARM instructions can be made to execute conditionally by postfixing
them with the appropriate condition code field.
This improves code density and performance by reducing the number of
forward branch instructions.
CMP r3,#0 CMP r3,#0
BEQ skip ADDNE r0,r1,r2
ADD r0,r1,r2
skip
By default, data processing instructions do not affect the condition code
flags but the flags can be optionally set by using “S”. CMP does not
need “S”.
loop
…
SUBS r1,r1,#1
BNE loop
if Z flag clear then branch
decrement r1 and set flags
Conditional Execution and Flags
18. 19
TM 19
39v10 The ARM Architecture
Condition Codes
Not equal
Unsigned higher or same
Unsigned lower
Minus
Equal
Overflow
No overflow
Unsigned higher
Unsigned lower or same
Positive or Zero
Less than
Greater than
Less than or equal
Always
Greater or equal
EQ
NE
CS/HS
CC/LO
PL
VS
HI
LS
GE
LT
GT
LE
AL
MI
VC
Suffix Description
Z=0
C=1
C=0
Z=1
Flags tested
N=1
N=0
V=1
V=0
C=1 & Z=0
C=0 or Z=1
N=V
N!=V
Z=0 & N=V
Z=1 or N=!V
The possible condition codes are listed below:
Note AL is the default and does not need to be specified
19. 20
TM 20
39v10 The ARM Architecture
Examples of conditional
execution
Use a sequence of several conditional instructions
if (a==0) func(1);
CMP r0,#0
MOVEQ r0,#1
BLEQ func
Set the flags, then use various condition codes
if (a==0) x=0;
if (a>0) x=1;
CMP r0,#0
MOVEQ r1,#0
MOVGT r1,#1
Use conditional compare instructions
if (a==4 || a==10) x=0;
CMP r0,#4
CMPNE r0,#10
MOVEQ r1,#0
20. 21
TM 21
39v10 The ARM Architecture
Branch : B{<cond>} label
Branch with Link : BL{<cond>} subroutine_label
The processor core shifts the offset field left by 2 positions, sign-extends
it and adds it to the PC
± 32 Mbyte range
How to perform longer branches?
28
31 24 0
Cond 1 0 1 L Offset
Condition field
Link bit 0 = Branch
1 = Branch with link
23
25
27
Branch instructions
21. 22
TM 22
39v10 The ARM Architecture
Data processing Instructions
Consist of :
Arithmetic: ADD ADC SUB SBC RSB RSC
Logical: AND ORR EOR BIC
Comparisons: CMP CMN TST TEQ
Data movement: MOV MVN
These instructions only work on registers, NOT memory.
Syntax:
<Operation>{<cond>}{S} Rd, Rn, Operand2
Comparisons set flags only - they do not specify Rd
Data movement does not specify Rn
Second operand is sent to the ALU via barrel shifter.
22. 23
TM 23
39v10 The ARM Architecture
The Barrel Shifter
Destination
CF 0 Destination CF
LSL : Logical Left Shift ASR: Arithmetic Right Shift
Multiplication by a power of 2 Division by a power of 2,
preserving the sign bit
Destination CF
...0 Destination CF
LSR : Logical Shift Right ROR: Rotate Right
Division by a power of 2 Bit rotate with wrap around
from LSB to MSB
Destination
RRX: Rotate Right Extended
Single bit rotate with wrap around
from CF to MSB
CF
23. 24
TM 24
39v10 The ARM Architecture
Register, optionally with shift operation
Shift value can be either be:
5 bit unsigned integer
Specified in bottom byte of another
register.
Used for multiplication by constant
Immediate value
8 bit number, with a range of 0-255.
Rotated right through even number of
positions
Allows increased range of 32-bit
constants to be loaded directly into
registers
Result
Operand
1
Barrel
Shifter
Operand
2
ALU
Using the Barrel Shifter:
The Second Operand
24. 25
TM 25
39v10 The ARM Architecture
No ARM instruction can contain a 32 bit immediate constant
All ARM instructions are fixed as 32 bits long
The data processing instruction format has 12 bits available for operand2
4 bit rotate value (0-15) is multiplied by two to give range 0-30 in steps of 2
Rule to remember is “8-bits shifted by an even number of bit positions”.
0
7
11 8
immed_8
Shifter
ROR
rot
x2
Quick Quiz:
0xe3a004ff
MOV r0, #???
Immediate constants (1)
25. 26
TM 26
39v10 The ARM Architecture
Examples:
The assembler converts immediate values to the rotate form:
MOV r0,#4096 ; uses 0x40 ror 26
ADD r1,r2,#0xFF0000 ; uses 0xFF ror 16
The bitwise complements can also be formed using MVN:
MOV r0, #0xFFFFFFFF ; assembles to MVN r0,#0
Values that cannot be generated in this way will cause an error.
0
31
ror #0
range 0-0xff000000 step 0x01000000
ror #8
range 0-0x000000ff step 0x00000001
range 0-0x000003fc step 0x00000004
ror #30
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Immediate constants (2)
26. 27
TM 27
39v10 The ARM Architecture
To allow larger constants to be loaded, the assembler offers a pseudo-
instruction:
LDR rd, =const
This will either:
Produce a MOV or MVN instruction to generate the value (if possible).
or
Generate a LDR instruction with a PC-relative address to read the constant
from a literal pool (Constant data area embedded in the code).
For example
LDR r0,=0xFF => MOV r0,#0xFF
LDR r0,=0x55555555 => LDR r0,[PC,#Imm12]
…
…
DCD 0x55555555
This is the recommended way of loading constants into a register
Loading 32 bit constants
27. 28
TM 28
39v10 The ARM Architecture
Multiply
Syntax:
MUL{<cond>}{S} Rd, Rm, Rs Rd = Rm * Rs
MLA{<cond>}{S} Rd,Rm,Rs,Rn Rd = (Rm * Rs) + Rn
[U|S]MULL{<cond>}{S} RdLo, RdHi, Rm, Rs RdHi,RdLo := Rm*Rs
[U|S]MLAL{<cond>}{S} RdLo, RdHi, Rm, Rs RdHi,RdLo := (Rm*Rs)+RdHi,RdLo
Cycle time
Basic MUL instruction
2-5 cycles on ARM7TDMI
1-3 cycles on StrongARM/XScale
2 cycles on ARM9E/ARM102xE
+1 cycle for ARM9TDMI (over ARM7TDMI)
+1 cycle for accumulate (not on 9E though result delay is one cycle longer)
+1 cycle for “long”
Above are “general rules” - refer to the TRM for the core you are using
for the exact details
28. 29
TM 29
39v10 The ARM Architecture
Single register data transfer
LDR STR Word
LDRB STRB Byte
LDRH STRH Halfword
LDRSB Signed byte load
LDRSH Signed halfword load
Memory system must support all access sizes
Syntax:
LDR{<cond>}{<size>} Rd, <address>
STR{<cond>}{<size>} Rd, <address>
e.g. LDREQB
29. 30
TM 30
39v10 The ARM Architecture
Address accessed
Address accessed by LDR/STR is specified by a base register plus an
offset
For word and unsigned byte accesses, offset can be
An unsigned 12-bit immediate value (ie 0 - 4095 bytes).
LDR r0,[r1,#8]
A register, optionally shifted by an immediate value
LDR r0,[r1,r2]
LDR r0,[r1,r2,LSL#2]
This can be either added or subtracted from the base register:
LDR r0,[r1,#-8]
LDR r0,[r1,-r2]
LDR r0,[r1,-r2,LSL#2]
For halfword and signed halfword / byte, offset can be:
An unsigned 8 bit immediate value (ie 0-255 bytes).
A register (unshifted).
Choice of pre-indexed or post-indexed addressing
30. 31
TM 31
39v10 The ARM Architecture
0x5
0x5
r1
0x200
Base
Register 0x200
r0
0x5
Source
Register
for STR
Offset
12 0x20c
r1
0x200
Original
Base
Register
0x200
r0
0x5
Source
Register
for STR
Offset
12 0x20c
r1
0x20c
Updated
Base
Register
Auto-update form: STR r0,[r1,#12]!
Pre or Post Indexed Addressing?
Pre-indexed: STR r0,[r1,#12]
Post-indexed: STR r0,[r1],#12
31. 32
TM 32
39v10 The ARM Architecture
LDM / STM operation
Syntax:
<LDM|STM>{<cond>}<addressing_mode> Rb{!}, <register list>
4 addressing modes:
LDMIA / STMIA increment after
LDMIB / STMIB increment before
LDMDA / STMDA decrement after
LDMDB / STMDB decrement before
IA
r1 Increasing
Address
r4
r0
r1
r4
r0
r1
r4
r0 r1
r4
r0
r10
IB DA DB
LDMxx r10, {r0,r1,r4}
STMxx r10, {r0,r1,r4}
Base Register (Rb)
32. 33
TM 33
39v10 The ARM Architecture
Software Interrupt (SWI)
Causes an exception trap to the SWI hardware vector
The SWI handler can examine the SWI number to decide what operation
has been requested.
By using the SWI mechanism, an operating system can implement a set
of privileged operations which applications running in user mode can
request.
Syntax:
SWI{<cond>} <SWI number>
28
31 24
27 0
Cond 1 1 1 1 SWI number (ignored by processor)
23
Condition Field
33. 34
TM 34
39v10 The ARM Architecture
PSR Transfer Instructions
MRS and MSR allow contents of CPSR / SPSR to be transferred to / from
a general purpose register.
Syntax:
MRS{<cond>} Rd,<psr> ; Rd = <psr>
MSR{<cond>} <psr[_fields]>,Rm ; <psr[_fields]> = Rm
where
<psr> = CPSR or SPSR
[_fields] = any combination of ‘fsxc’
Also an immediate form
MSR{<cond>} <psr_fields>,#Immediate
In User Mode, all bits can be read but only the condition flags (_f) can be
written.
27
31
N Z C V Q
28 6
7
I F T mode
16
23 8
15 5 4 0
24
f s x c
U n d e f i n e d
J
34. 35
TM 35
39v10 The ARM Architecture
ARM Branches and Subroutines
B <label>
PC relative. ±32 Mbyte range.
BL <subroutine>
Stores return address in LR
Returning implemented by restoring the PC from LR
For non-leaf functions, LR will have to be stacked
STMFD
sp!,{regs,lr}
:
BL func2
:
LDMFD
sp!,{regs,pc}
func1 func2
:
:
BL func1
:
:
:
:
:
:
:
MOV pc, lr
35. 36
TM 36
39v10 The ARM Architecture
Thumb
Thumb is a 16-bit instruction set
Optimised for code density from C code (~65% of ARM code size)
Improved performance from narrow memory
Subset of the functionality of the ARM instruction set
Core has additional execution state - Thumb
Switch between ARM and Thumb using BX instruction
0
15
31 0
ADDS r2,r2,#1
ADD r2,#1
32-bit ARM Instruction
16-bit Thumb Instruction
For most instructions generated by compiler:
Conditional execution is not used
Source and destination registers identical
Only Low registers used
Constants are of limited size
Inline barrel shifter not used
36. 37
TM 37
39v10 The ARM Architecture
Agenda
Introduction
Programmers Model
Instruction Sets
System Design
Development Tools
37. 38
TM 38
39v10 The ARM Architecture
Example ARM-based System
16 bit RAM
8 bit ROM
32 bit RAM
ARM
Core
I/O
Peripherals
Interrupt
Controller
nFIQ
nIRQ
38. 39
TM 39
39v10 The ARM Architecture
AMBA
Bridge
Timer
On-chip
RAM
ARM
Interrupt
Controller
Remap/
Pause
TIC
Arbiter
Bus Interface
External
ROM
External
RAM
Reset
System Bus Peripheral Bus
AMBA
Advanced Microcontroller Bus
Architecture
ADK
Complete AMBA Design Kit
ACT
AMBA Compliance Testbench
PrimeCell
ARM’s AMBA compliant peripherals
AHB or ASB APB
External
Bus
Interface
Decoder
39. 40
TM 40
39v10 The ARM Architecture
Agenda
Introduction
Programmers Model
Instruction Sets
System Design
Development Tools
40. 41
TM 41
39v10 The ARM Architecture
The RealView Product Families
Debug Tools
AXD (part of ADS)
Trace Debug Tools
Multi-ICE
Multi-Trace
Platforms
ARMulator (part of ADS)
Integrator™ Family
Compilation Tools
ARM Developer Suite (ADS) –
Compilers (C/C++ ARM & Thumb),
Linker & Utilities
RealView Compilation Tools (RVCT) RealView Debugger (RVD)
RealView ICE (RVI)
RealView Trace (RVT)
RealView ARMulator ISS (RVISS)
41. 42
TM 42
39v10 The ARM Architecture
ARM Debug Architecture
ARM
core
ETM
TAP
controller
Trace Port
JTAG port
Ethernet
Debugger (+ optional
trace tools)
EmbeddedICE Logic
Provides breakpoints and processor/system
access
JTAG interface (ICE)
Converts debugger commands to JTAG
signals
Embedded trace Macrocell (ETM)
Compresses real-time instruction and data
access trace
Contains ICE features (trigger & filter logic)
Trace port analyzer (TPA)
Captures trace in a deep buffer
EmbeddedICE
Logic