1. 1
UNIVERSITY OF MASSACHUSETTS
LOWELL
James B. Francis College of Engineering
Department of Electrical & Computer
Engineering
Advanced VLSI Design
Assignment 3
Spring 2015
Name of the Student
Riddhi Shah
Name of the Professor
Martin Margala Ph.D.

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Table of Contents
1. Introduction
2. Design Analysis and Schematic Design
3. Simulation Results
4. Result Analysis and Discussions
5. Conclusion

3. 3
Introduction
 Low power designs, for which CMOS is the primary technology. Low power
design has become the major challenge of present chip designs as leakage
power has been rising with scaling of technologies. With increasing chip
densities, leakage power has become dominant in memory design. To achieve
low power operation we have chosen 6T SRAM cell to design 16-bit memory of
4wordsx4bits. This work targets reduction ofpower dissipation in SRAM system
during both active and idle mode of operations.
 The power dissipation consists of dynamic and static power. Dynamic power
consumption was previously the single largest concern for low-power chip
designers since dynamic power accounted for 90% or more of the total chip
power. However, as the feature size shrinks, static power has become a great
challenge for current and future technologies.
Figure 1 Memory array architecture of 4x4 SRAM

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 Suppressing the leakage current in memories is critical in low Power Design. By
reducing the standby voltage (VDD) to its limit, which is the Data Retention
Voltage (DRV) leakage power can be substantially reduced. This assignment
explores how low DRV canbe in a standard low leakage SRAM module through
which still the circuit will work. In SRAM Design, the Data Retention Voltage
(DRV) defines the minimum VDD under which the data in a memory is still
preserved. Also, the assignment focuses on minimizing the static power using
Multi divided word line technique. It compares the difference between the
static powers consumed by traditional SRAM Array to Multi Divided Word line
SRAM Array.
Figure 2 6T SRAM cell Figure 3 Block Diagram of 4x4 SRAM

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Design Analysis
 SRAM cell:
The fundamental building block of a static RAM is the SRAM memory cell. A 6T
SRAM is commonly used in practice. Such a cell uses a single Word line and both
true and complementary bit lines (bit & bitb). The complementary bit line is often
called bitb. The cell contains a pair of cross-coupled inverters and an access
transistor foreachbit line. True and complementary versions ofthe data are stored
on the cross coupled inverters. If the data is disturbed slightly, positive feedback
around the loop will restore it to VDD or GND. The Word line is asserted to read or
write the cell. The nMOS access transistors are best at passing '0's. For reads, the
bitlines are initially pre charged high and the SRAM cell pulls one down through the
access transistor. For writes, the bitline or its complement is actively driven low
and this low value over powers the cell to write the new value. Careful choices of
transistor sizes are necessary for correct operation. The 6T cell achieves its
compactness at the expense of more complex peripheral circuitry for reading and
writing the cells. This is a good tradeoff in large RAM arrays where the cell size
dominates the area.
Names Width(nm) Length(nm)
T0=T1 480 120
T2=T3 480 120
T4 720 120
T5 720 120
Table 1: Sizing of the transistors

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Figure 4: 6T Single SRAM cell

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Figure 5: 4x4 Array of SRAM

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Figure 7: Sense Amplifier Figure 8: Write Driver
Figure 9: Read Operation Waveform

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Figure 10: Write Operation Waveform
 Pre charging:
One pre charging circuit is connected for every column to pre charge the
complementary bit-lines, BIT and BITN, to pre charged “1” state during inactive
state of memory as shown in fig. 3. The signal PRECHARGE is used for this
purpose. The pre charge circuit is isolated from the bit-lines during the memory
write and read operation.
Figure 11: Precharge Circuit

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 Address decoding:
The proposed SRAM system has storage capacity of 4 words of 4 bit each. To
address these words in a unique manner, 2: 4 row decoders are used. This decoder
can accept addresses ranging from 00 to 11. According to the address input the
address decoder activates one of the rows by asserting one of the word lines and all
the other word address lines remain low. The 4 words are selected by this 2:4
decoder. The address bits A2A1 determine the word to be selected for data write or
read operation. Only one of the four address lines is activated in any given time. The
4 selection lines WL_0 to WL_3 are connected to 4 rows of the 4x4 memory array.
Figure 12: 2:4 Decoder
 Data Retention Voltage:
As mentioned in the introduction, DRV defines the minimum VDD under which the
data in a memory unit is still preserved. The circuit structure of a 6T SRAM cell is
shown in Fig.1. When VDD is reduced to DRV, all six transistors are in the sub-
threshold region, thus the capability of SRAM data retention strongly depends on
the (sub- Vth) current conduction behavior. Inorder to understand the low voltage
data preservation behavior of SRAM and potential for leakage saving through
minimizing standby VDD analytical models are developed. The voltage transfer
curves (VTC) for different VDD values are being plotted and the simulation shows
that assigning a guard band of 100mV above DRV for standby VDD gives 250mV in
SRAM cell Static Noise Margin (SNM) and that the SNM degrades linearly with the
VDD and that the SNM degrades linearly with the VDD guard band. Here, the SNM

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is defined as the edge of the maximum square that can fit into the cross sectionof
the VTC diagram of the cross coupled inverters.
Figure 13: Voltage Transfer Curve (Butterfly Curve)
Leakage Current:
Figure 14: Leakage Current Waveform
 From the waveform we can infer that the DRV would be nearly to 750mV

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 Voltage down Converter:
A Voltage downConverter is used to convert the Reference Voltage to DRV voltage.
When a standby signal is provided, the VDD will be switched to sub-Voltage Vth. A
reference voltage of 1.2V is converted to DRV of 750mV. When the SRAM is in
active mode, the voltage supplied to the cell is normal VDD. When the SRAM is
changed to Active mode, the switching of the Voltage takes place fromnormal VDD
to DRV.
The standby signal when high activates the DRV and when is low supplies the
normal voltage to the SRAM cell. The Voltage DownConverter is attachedto SRAM
Cell using Transistor as shown in Fig Waveform of Voltage Down Converter is
shown in Fig The standby signal indicates the operating mode of the SRAM cell.
Figure 15: Voltage down converter with pass transistor

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Simulation Results
Fig. 8 explains the SRAM Array when operated. Initially when Precharge signal is
low, the bitlines are precharged high and left floating. When Wordline (Wl0) and
Data line (D0) are high and Write signal is low, the SRAM operates in Read mode.
Thus the Data present in A is read onbitline and finally read by the sense amplifier
in Dataout0. Dataout0 indicates the data read on the SRAM Cell. When Wordline
(Wl0) and Data line (D0) are high and Write signal is high, the data is written into
the SRAM Cell. In this design, anyone of the Wordline and Dataline are selected
using Rowand Column Decoders.There are 3 inputs to eachDecoder and 4 outputs
of each decoder. The outputs of Row decoder are Wl0, Wl1, Wl2 and Wl3. The
outputs of Column Decoder are D0, D1, D2 and D3. It can be observed from Figure
8, when one of the outputs of different decoders are high, the other outputs of
respective decoders are low. The Wordline Wl0 acts as input to the Wordlines of
four different SRAM cells, which are onthe same row.Similarly eachSRAM Cell has
same input of Wordline present in same row, and each SRAM cell has the same
Dataline present in same column.
Table.2 explains the operationof 4X4 SRAM Array. There are 16 SRAM Cells in this
Array and each cell can be identified in with respective Wordline and Dataline.
Multi-divided Word line:
In a traditional SRAM Array, when one wordline of one cell is activated, the wordlines
of the other SRAM cells present in the same row also gets activated thus consuming
more power. Hence, in order to activate only one SRAM cell, the concept of multi
divided Wordline and multi divided Dataline are introduced. However, due to time
constraint, multi divided Wordline concept is only done in this assignment.
In this multi-divided wordline, the outputs of the Row Decoders (Wl0, Wl1, Wl2 and
Wl3) are not directly sent to inputs of SRAM Cells but are passed through nMOS
Transistors which acts as switch. The Wordline of the SRAM cells are high when both
their respective Wordlines (addresses) and Datalines (Read/Write) are high. Figure
below indicates the design of Multi divided Wordline. So for the multi divided
Wordline SRAM Array, there are 16 different inputs to the Wordlines (Wl00, Wl01 and
Wl02…. Wl15) where a traditional SRAM Array has only 4 Wordline (Wl0, Wl1, Wl2,
and Wl3) input. However, the column circuitry, which is comprised of Sense Amplifier,
Read/Write Circuit, is same for the SRAM Cells present in single column.

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Figure 16: One Cell multidivided word line Figure 17: 4x4 multidivided word line
Results Analysis
Table 3 indicates the static power consumed by different models of SRAM. The static
power consumed by one SRAM Cell when working under normal Voltage is 233.52
nW. The Static power consumed by one SRAM cell when operating under DRV is very
less when compared to that of static power consumed by the same SRAM cell when
operating under normal voltage. The power consumed by traditional 4X4 SRAM
Array is 430.8 µW. The Power consumed by Multi Divided Wordline SRAM Array is
155.8 µW.
Different Models Static Power Consumed
SRAM under normal Vdd 232.23 nW
SRAM cell under DRV 10.9 nW
Traditional 4x4 SRAM Array 730.8 µW
Multi-divided Word line Array 155.8 µW

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Conclusion
The static power consumed by SRAM Cell when working under DRV is very much less
when compared to Static Power consumed by the same SRAM Cell when operating
under normal Voltage. It can also be inferred that the power consumed by traditional
4X4 SRAM Array can be reduced when the SRAM Array is arranged in Multi Divided
Wordline Technique.