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  1. 1. Design and Implementation of VLSI Systems (EN1600) Lecture 24: Computer-Aided Design using Tanner ToolsS. Reda EN1600 SP’08
  2. 2. S-Edit: A tool for schematic entryS. Reda EN1600 SP’08
  3. 3. Add a library (SCMOS) to your designS. Reda EN1600 SP’08
  4. 4. The library content (cells show up)S. Reda EN1600 SP’08
  5. 5. Add a view to your designS. Reda EN1600 SP’08
  6. 6. You can draw your circuit in the view canvasS. Reda EN1600 SP’08
  7. 7. How to add components to the view?S. Reda EN1600 SP’08
  8. 8. Create an input portS. Reda EN1600 SP’08
  9. 9. Create busses (bundles) Wire Wire (net) (net) labelS. Reda EN1600 SP’08
  10. 10. Then label the individual wires and the busesS. Reda EN1600 SP’08
  11. 11. Repeat for other signals. Make sure to label the input/output pads correctly Check your schematicS. Reda EN1600 SP’08
  12. 12. Export your netlistS. Reda EN1600 SP’08
  13. 13. Switch to L-Edit Load the setup and libraryS. Reda EN1600 SP’08
  14. 14. P & R setupS. Reda EN1600 SP’08
  15. 15. Then P & RS. Reda EN1600 SP’08
  16. 16. Everything gets done for you! Where are the pins?S. Reda EN1600 SP’08
  17. 17. Make things easier by specifying pin locationsS. Reda EN1600 SP’08
  18. 18. Redo P & R → the IO pads to the boundary You can extract to SPICE and continue as usualS. Reda EN1600 SP’08
  19. 19. Hierarchical design in S-Edit Create a symbol out of your register schematicS. Reda EN1600 SP’08
  20. 20. Now create a new view schematic in your design (slide 5)S. Reda EN1600 SP’08
  21. 21. Start adding your registers as instancesS. Reda EN1600 SP’08
  22. 22. Then interconnect your placed componentsS. Reda EN1600 SP’08
  23. 23. Now P & R the whole thingS. Reda EN1600 SP’08
  24. 24. Overall flow design entry Schematic capture using S-Edit IC layout/ P&R Cell library area using L-Edit SPICE Verification timing/ powerS. Reda EN1600 SP’08
  25. 25. Final project • Your project should fit on a 1.5 x 1.5 mm 40-pin MOSIS “TinyChip” fabricated in a 0.5 µm AMI process your project must not exceed 5000 x 5000 λ including I/O pads. • Therefore, the core of your project must fit in a 3400 x 3400 λ box and have no more than 40 pins. Six pins should be dedicated to VDD/GND, so only 34 are available as I/Os. • Fabrication schedule is 6th of June. Only projects that have demonstrated to work perfectly have a chance to get fabricated. Chips come during the Fall so you have to commit to testing them when they come back. • We might be limited to one design submission, so priority will be given to projects that are perfect (DRC is 100% OK, electrical verification is 100% OK, etc).S. Reda EN1600 SP’08
  26. 26. Project logistics • There is a project report and presentation per group at the last lecture of the semester (5/5). • Class project is worth 20% of your grade. You are allowed to work in groups of 2 or 3. – Grading: • 15% specification • 20% design schematics • 10% layout • 30% verification and SPICE simulations • 10% final report organization • 15% presentationS. Reda EN1600 SP’08
  27. 27. Class project suggestions and milestones • Possible projects: small programmable FPGA, cache memory, error detection and correction circuits, a small CPU, digital signal processing circuits, high speed arithmetic circuits, etc. • Milestones: – Wed April 9: Team and project finalization – Wed April 16: Specifications for your project well documents (block diagrams, functionality specification using pseudo-code or C/MATLAB, I/O pads, chip area estimation, etc) – Wed April 23: schematics and layouts are finalized – Wed April 30: simulations and verification is finalized – Mon May 5: Report and final presentationS. Reda EN1600 SP’08