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Design and Implementation of VLSI Systems
                (EN1600)
     Lecture 26: Datapath Subsystems 2/4
Last lecture we designed a carry-ripple
adder


                                                   PG summary




• For a full adder, define what happens to carry
   – Generate: Cout = 1 independent of C
       • G=A•B
    – Propagate: Cout = C
       • P=A⊕B
    – Kill: Cout = 0 independent of C
        • K = ~A • ~B
Group carry calculations
                                          i         k k-1   j




 The carry into bit i is the carry-out of bit i-1


 The sum is equal to
Group generate
                 i   k k-1   j
Carry-ripple adder revisited
          A4        B4   A3        B3   A2        B2   A1        B1   Cin



                                                                                  1: Bitwise PG logic
               G4   P4        G3   P3        G2   P2        G1   P1     G0   P0



                                                                                  2: Group PG logic


                          G3:0          G2:0            G1:0          G0:0

                              C3             C2             C1          C0
                                                                                  3: Sum logic




               C4

        Cout        S4             S3             S2             S1
Carry-ripple adder revisited
            A4        B4   A3          B3   A2          B2   A1          B1   Cin




                 G4   P4        G3     P3        G2     P2        G1     P1     G0     P0




                                G3:0             G2:0             G1:0          G0:0

                                C3               C2               C1            C0




                 C4

          Cout        S4               S3               S2               S1


  The critical path now proceeds through a chain of AND-OR
  gates rather than a chain of majority gates
8-bit adder/subtractor
                           add/subt                   C0=Cin
   Subtraction – complement               A0   1-bit
    all subtrahend bits (xor                    FA         S0
    gates) and set the low            B0          C1
    order carry-in                         A1   1-bit
                                                FA         S1
                                      B1
                                                  C2
                                           A2   1-bit
                                                FA         S2
                                      B2          C3




                                                ...
                                                      C7
                                           A7   1-bit
                                                FA         S7
                                      B7
                                                      C8=Cout

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Lecture26

  • 1. Design and Implementation of VLSI Systems (EN1600) Lecture 26: Datapath Subsystems 2/4
  • 2. Last lecture we designed a carry-ripple adder PG summary • For a full adder, define what happens to carry – Generate: Cout = 1 independent of C • G=A•B – Propagate: Cout = C • P=A⊕B – Kill: Cout = 0 independent of C • K = ~A • ~B
  • 3. Group carry calculations i k k-1 j The carry into bit i is the carry-out of bit i-1 The sum is equal to
  • 4. Group generate i k k-1 j
  • 5. Carry-ripple adder revisited A4 B4 A3 B3 A2 B2 A1 B1 Cin 1: Bitwise PG logic G4 P4 G3 P3 G2 P2 G1 P1 G0 P0 2: Group PG logic G3:0 G2:0 G1:0 G0:0 C3 C2 C1 C0 3: Sum logic C4 Cout S4 S3 S2 S1
  • 6. Carry-ripple adder revisited A4 B4 A3 B3 A2 B2 A1 B1 Cin G4 P4 G3 P3 G2 P2 G1 P1 G0 P0 G3:0 G2:0 G1:0 G0:0 C3 C2 C1 C0 C4 Cout S4 S3 S2 S1 The critical path now proceeds through a chain of AND-OR gates rather than a chain of majority gates
  • 7. 8-bit adder/subtractor add/subt C0=Cin  Subtraction – complement A0 1-bit all subtrahend bits (xor FA S0 gates) and set the low B0 C1 order carry-in A1 1-bit FA S1 B1 C2 A2 1-bit FA S2 B2 C3 ... C7 A7 1-bit FA S7 B7 C8=Cout