This document appears to be an exam for a digital circuits course, as it covers topics like CMOS inverters, MESFETs, MOSFETs, finite state machines, logic minimization techniques, and hardware description languages. The exam consists of 20 multi-part questions worth a total of 100 marks. Students are instructed to answer any 5 full questions from the list provided.

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Max. Marks:100
Note: Answer $rry FIVE full questions.
Explain CMOS inverter using transfer characteristic and describe aspect ratio with relevant
expression. (10 N1arks)
Using switch logic, write CMOS NAND gate and CMOS NOR gate diagram. (06 Marks)
Compare CMOS and BiCMOS technologies. (04 Marks)
Explain MESFET under bias of Vo below pinch off and bias at pinch off with its current -
vo ltage characteristic. (10 Marks)
Derive an expression for the pinch-ofTvoltage in MESFET with an active layer thickness of
Describe the MIS system under three different biased conditions (i.e accumulation, depletion
and inversion region). (12 Marks)
Calculate the threshold voltage (Vr) for a n-channel MIS device given the following
Na : l0l7 cm'', Q,
: 10" alcm2, d: 20nm and Q*, : -0.95 V. (08 Marks)
With a neat diagram, explain two dimensional potential profile for a long channel MOSFET
't' .
Differentiate between MESFE,T arrd MODFET.
device and short channel MOSFET device.
Describe the processing challenges to further CMOS miniaturization.
Explain the differerlces betwccn bulk MOSFET and SOI MOSFET
depletion region.
Discuss :
i) Conventional Vs tactile computation
ii) Molecular and biologicai computing.
(06 Marks)
(04 Marks)
(12 Marks)
(08 Marks)
in the gate controlled
(10 Marks)
a.
b.
a.
b.
a. Explain RC delay line using long silicon trine using suitable rnathematrcal analysis.
b. What are super buffers? Explain inverting and non inverting nMOS super butfers.
a. Describe 4 input taliy circuits.
b. Realize (AB + CD) : y rn i) NN,'IOS ii) CMOS technology, using static AOI.
c. Write a note on nMOS multiplxers.
Discuss :
a. Regularity
b. Modularity
c. Locality
d. Standard ceil
e. Full custom design.
(10 Marks)
(10 Marks)
(10 Marks)
(10 Marks)
(05 Marks)
(05 Marks)
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(20 Marks)

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Synthesis
Time: 3 hrs.
14EVE41
(10 Marks)
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(08 Marks)
(06 Marks)
(08 Marks)
(04 Marks)
(10 Marks)
(10 Marks)
(08 Marks)
the algorithmic and rule - based binding
(12 Marks)
M.Tech. Degree Examination, June/July 2016
and Optimization of Digital Gircuits
Max. Marks:100
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c. For the graph in figure, find the minimum vertex cover.
D Expand ii) Reduce
Explain ATPG.
iii) Irredundant iv) Essentials.
With suitable example, explain the rule based system for logic optimization.
Write the pseudocode for the ASAP and ALAP scheduling algoiltt *.
Note: Answer any FIVE.fall questions"
Briefly explain on the architectural level, logic level and geometrical level synthesis with
relevant figures. (10 Marks)
With necessary diagrams and notations discuss on directed and undirected graphs. (10 Marks)
Give the structural and behavioural representation of Half Adder in rfUOt. (05 Marks)
For a function f : (ab + bc + ac), find the Boolean difference , consensus and smoothing
3a.
b.
c.
4a.
b.
Fig.Q2(c)
Write the Drjkstra algorithm.
Compare the different hardware description languages used for synthesis.
Explain the following abstract models :
D Structures ii) Logic Networks.
What do you mean by tautology? Find if the function f : ab * ac * a'is a tautology.
Explain the following operators for logic minimization ,
t08 Marks)
c.
a.
b.
a.
b.
With neat diagrams, explain the different types of finite state machine decompositions.
(08 Nlarks)
Discuss on Don't care conditions in synchronous networks. Also define input
controllability, output observability and internal observability. (12 Marks)
a. Explain Loop folding with an example.
b. Explain the rule - based library binding. Compare
approaches.
Write short notes on :
a. ILP model for scheduling.
b. LUT FPGA.
c. Microelectronic Design Style.
d. Hu's Algorithm. (20 Marks)