Intro to FPGA's I presented to the Melbourne PC users group on 11th April 2018. I demo'ed blinking LEDS on a Zybo board using bare metal and then a memory mapped application process.

1. Why a Zynq should
power your next
project
(intro to FPGA’s by Mark Smith)

2. Who
remembers
this?

3. “The video display generator of the ZX80 used minimal
hardware plus a combination of software to generate a video
signal. This was an idea that was popularised by Don
Lancaster in his 1978 book The TV Cheap Video Cookbook and
his "TV Typewriter".[7] As a result of this approach the ZX80
could only generate a picture when it was idle, i.e. waiting for
a key to be pressed.” Wikipedia Entry on ZX80

4. We offloaded video
to CGA, HGC, EGA,
VGA etc.
Separate hardware
cards to take over the
job from software

5. But it’s still
hardware rigidly
implementing a
control algorithm
What if there was a way to
generalise it? In the end it’s just
digital logic right?

6. Combinational
Logic is a truth
table
Sequential logic adds some state
memory
Image source: https://www.electronics-tutorials.ws

7. Some clever
people took that
idea...
This is the base unit of an FPGA:
a combinational logic block and a
flip flop, with a MUX to select the
output
4 LUT
MUX
D Q
CLK
A Logic Block in an FPGA

8. ...added a
massive
interconnect,
and call it an
FPGA
They created a massive
interconnect between a series of
logic blocks that are
programmable in the field.
(they also added DSP elements,
BRAM elements)

9. That Hercules card
implemented in an
FPGA could have
been rewritten as a
VGA card with a
software update

10. FPGAs can
implement a
‘soft core’
microcontroller
by uploading
Intellectual
Property (IP)

11. There is an IP industry for whatever you want

12. Then there’s
Zynq
Hard-IP Dual core ARM A9 with
programmable logic.

13. Perrone
Autonomous
Vehicles
Xilinx for control systems and
computation algorithms
Play the Vid

14. 3D sensing cameras
“Real time depth computation… 2.1
billion correspondence matches per
second… generate 15 million points a
second of 3D data … 1/10th the power
[of a ] normal processor.”

15. CV, Machine
Learning and
sensor fusion
On one chip: Zynq Ultrascale+
MPSoC device using reVISION
stack

16. Back to earth….
What can I do?

17. Entry level boards
Zybo - $280
Microzed - $290

18. Blinking LED’s
Bare Metal

19. Exercise 1B
The Zynq Book - Tutorials

20. The system block
design in Vivado

21. Hardware Platform Specification

22. Board Support Package

23. A Quick note on linux with usb serial
Cd
~/xilinx/Vivado/2017.4/data/x
icom/cable_drivers/lin64/inst
all_script/install_drivers/
sudo ./install_drivers
https://forums.xilinx.com/t5/Embedded-Development-Tools/issues-connecting-to-usb-jtag-on-zybo-under-linux/td-p/675162

24. The GPIO LEDs example code
(from exercise 1C file download)

25. Embedded Linux
Yocto or Petalinux for a custom
linux distribution
Linaro (and probably others) for
pre existing linux distro

26. Accessing
memory
mapping on
Linux
User app accessing memory
User space drivers
Kernel space drivers
Kernel space
RAM (where
the AXI
interface is
kept)
User
Process
Memory
mmap()

27. Blinking LEDS: Linux
petalinux-create --type project --name first-lx --template zynq
Petalinux-config --get-hw-description -p first-lx
Go to image and packaging, select rootfs to be sd-card
Petalinux-build -p first-lx
petalinux-package --boot --format BIN --fsbl images/linux/zynq_fsbl.elf --fpga
images/linux/first_zynq_system_wrapper.bit --u-boot
petalinux-config -c rootfs
petalinux-create -p first-lx -t apps -n gpio-dev-mem-test
sudo pax -rvf rootfs.cpio
axi-gpio-test -g 41200000 -c 2 -o 255

28. Remember IP?
You can make your
own.

29. Vivado HLS
Takes c/c++ code and
implements the equivalent
circuit in the FPGA. Accelerating
it enormously and with lower
power requirements that other
solutions

30. Zynq Book 3C.
Cd /home/mark/dev/tut3A
vivado_hls -p matrix_mult_prj

31. HLS accelerates
control or
computation centric
algorithms

32. The IP is in the catablog and played
like any other IP

33. People are using it
for onboard image
processing in
satellites
DFE in this table is a cluster of
FPGA’s running an algorithm. The
takeaway is that Zynq used way less
power, and had a performance per
pixel that ran third to some serious
server hardware (way faster than
other ARM implementations)
“A Scalable Dataflow Accelerator for Real Time Onboard
Hyperspectral Image Classification”, Wang et al, 2016

34. What I’m using it
for
Multi-algorithm Digital Currency
Miner.
I’m intending to use Vivado HLS to
implement a miner algorithm, and
reconfigurability to switch
algorithms IN HARDWARE on the
fly.

35. Milestones
2017 2018
Nov 2017
Blinking LEDS on Linux
Feb 2018
CPU multi miner running
on Zynq. (but not using
fabric)
Next
Cryptonite algorithm
accelerated through HLS
Later
Other algorithms, ‘what to
mine’ like functionality to
decide when to switch

36. Simulink models can
generate VHDL code

37. Learning resources
The ZYNQ book