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GigaIO: The March of Composability Onward to Memory with CXL
- 1. The March of Composability Onward to Memory with CXL Alan Benjamin 1 Infrastructure Without Compromise ©2023 | GIGAIO |
- 2. THE MARCH OF COMPOSABILITY WITH GIGAIO 2 FabreX with CXL FabreX Today Legacy Networks ©2023 | GIGAIO |
- 3. 10X Better Latency - Sub-Microsecond Interconnect FABREX DRIVES OUT LATENCY TO DELIVER COMPOSITION PCIe/CXL Server 1 PCIe to Network translation NW Physical layer Server 2 Enet/IB Network Switch FabreX™ Network Adapter Network Adapter Storage GPUs FPGAs PCIe/CXL Storage GPUs FPGAs PCIe to Network translation NW Physical layer Processor Processor The Only Routable PCIe/CXL Network Throughout the Rack to Connect Both Resources and Servers ©2023 | GIGAIO | No translations, no buffers, no kernel calls – NOTHING to slow performance, reduce flexibility, or increase complexity and cost
- 4. ©2023 | GIGAIO | 4 MEMORY TIERS – WHERE YOU THINK IT IS TODAY Register Cache Main Memory Disaggregated Memory SSD HDD Attached to CPU Source: Hot Chips 2022 Network Attached 0.2ns 1–40ns 80-140ns 2-4μs 50-100μs 3-10ms
- 5. ©2023 | GIGAIO | 5 MEMORY TIERS – REALLY WHERE IT IS TODAY Register Cache Main Memory Attached to CPU Network Attached 0.2ns 1–40ns 80-140ns 2-4μs 50-100μs 3-10ms FabreX Disaggregated Memory 500ns-1.5μs HDD SSD Disaggregated Memory
- 6. ©2023 | GIGAIO | 6 KEY DESIGN ASPECTS OF CXL MEMORY CPU DDR CPU DRAM CPU DRAM DRAM DRAM DRAM DRAM LPDDR NVM CXL With CXL Today Without CXL CPU Interconnect 32GB/s per link 38.4 GB/s per Channel ~100ns DRAM ~180ns CPU 38.4 GB/s per Channel ~100ns DRAM CXL 64GB/s per x16 link ~170-250ns DRAM CXL Controller CXL moves memory to a serial comm link and creates Controller Goal is for CXL Memory to be equal in perf to 2nd processor memory DRAM DRAM DRAM Frees size and type from CPU, potentially allowing much: - Larger amounts of memory - Cheaper memory
- 7. ©2021 | GIGAIO | CONFIDENT IA L 7 Direct Attached Add Capacity Add Memory variety CXL 1.1 2H23 to 1H24 Pooled Memory Flexible allocation CXL 2.0 Shared Memory Flexible allocation CXL 2.0+ mid24 to 1H25 Fabric Memory Scale CXL 3.0 2026+ (pulling in?)
- 8. ©2023 | GIGAIO | 8 MEMORY TIERS – TOMORROW WITH CXL Register Cache Main Memory CXL Memory with DRAM Disaggregated Memory SSD HDD Attached to CPU CPU Independent Network Attached 0.2ns 1–40ns 80-140ns 170-250ns 300ns-1μs 2-4μs 50-100μs 3-10ms FabreX Disaggregated Memory 500ns-1.5μs High Latency Memory CXL other memory – NVMem, low cost
- 9. ©2023 | GIGAIO | 9 MEMORY TIERS – KEY ISSUES/CONSIDERATIONS Register Cache Main Mem CXL with DRAM CXL other memory Disaggregated Memory SSD HDD FabreX Disaggregated Memory High Latency Memory Key considerations for future adoption of CXL Operating System support for a new tier of memory Tension between performance and sharing (pooled or shared memory) Larger sharing could lead to more services, aka like storage If includes separate boxes – will add latency for switches, adapters, cables Coherency exponentially increases complexity – drives smaller “zones”
- 10. ©2023 | GIGAIO | 1 0 CXL MEMORY WILL (PROBABLY) BE THE FUTURE Register Cache Main Mem CXL with DRAM CXL other memory Disaggregated Memory SSD HDD FabreX Disaggregated Memory High Latency Memory CXL memory is an exciting new development Opens the door to much larger memory models for in-memory computing and much larger data sets. Lots of discussion about using less memory – but history says otherwise Lots of work to be done – and it will take time to build production ready solutions Experimentation and research started
- 11. 1 1 Shared Storage Servers DPU/NIC FPGAs Accelerator Pooling Appliances GPUs FabreX Memory Fabric Shared Memory ©2023 | GIGAIO | Focused on the best performance, greatest agility, and lowest cost Uniquely Handles All Compute Side Traffic GIGAIO UNITES PCIe & CXL UNDER A COMMON CONTROL PLANE Open Platform based on Industry Stds; Integrated with Leading Mgmt SW FabreX Memory Fabric Industry standard Redfish APIs PCIe + CXL PCIe + CXL
- 12. The Open AI Infrastructure Company 1 2 www.gigaio.com
Editor's Notes
- Now you may have heard of composability in the past. It has been around for a while. One of the key benefits of FabreX is composing resources to a system. Now FabreX has taken composability and brought it to a whole new level. <click> Solutions from HPE, Dell and others made composability a thing by composing storage. Now composing storage is not hard because storage doesn’t operate at the performance levels of anything else on this list. This allows the OEMs to compose across conventional fabrics such as Ethernet. <click> GigaIO can not only compose Storage, but everything on this list. When it comes to memory, today GigaIO can grant access to remote systems’ unused memory or allow multiple servers to share memory. <click> In the near future, this benefit will grow with the inclusion of CXL. GigaIO joined the CXL consortium from the beginning as a Contributing Member. the GigaIO software has been designed to include CXL capabilities and GigaIO already has memory-mapping specific APIs designed to make migration seamless.