The document discusses an evolutionary approach to standard cell design aimed at automating the design process to reduce costs and time associated with creating essential building blocks of VLSI chips. It highlights the challenges of traditional design methods and presents a new methodology for generating layouts in parallel with schematics. The research emphasizes the importance of fitness functions in evaluating design correctness and connectivity while acknowledging current limitations in handling complex designs.

1. An Evolutionary approach to Standard Cell Design: a proof of concept Anil Bahuman Artificial Intelligence Center University of Georgia July 2001

5. Research Goal Truth Table Layout with “minimum” area “ Schematic and layout are designed in parallel” Explore possibility of automating the design of simple logic standard cells by exploring design spaces not considered by human designers 1 0 1 0 0 1 Out In

6. Standard Cell Design Building blocks for chips. Frequently used logics. NAND, full adder, latch etc. Costly (time + money) to redesign. Can we design on-the-fly? Standard cells are building blocks of frequently used logics employed in VLSI Design. Examples include NAND, Full Adder, Latch and Inverter. These libraries are typically designed by hand in a very costly and time consuming process. One of the major challenges is the migration of standard cell layouts every time there is a change in the process. There is a strong need for automation alternatives.

7. Design Example

8. A Transistor in MAGIC

9. Error tiles indicating DRC Errors

10. An Inverter in MAGIC Lambda, cell limits, labels, template, inputs, output, gate, terminals, wires, poly, contacts, 3I - 1O

11. SPICE simulation of the Inverter

12. Research Goal

13. Research Goal – Inverter Truth Table Layout with “minimum” area “ Schematic and layout are designed in parallel” 1 0 1 0 0 1 Out In

14. Why Is This Worth Our Efforts? EDA is a multi-billion dollar industry On-the-fly vs. Compaction Traditional methods are schematic-dependent In our knowledge GAs have not been used for the design of standard cells

15. Architecture

16. architecture MAGIC SPICE Modified GADO (DRC ERRORS , AREA) (CORRECTNESS) DESIGN ENGINE EVALUATOR DESIGN RULE CHECKER CIRCUIT SIMULATOR Fitness module (CIRCUIT FILE)

17. Errors in a Design : 1 Shorted Labels Overlapping transistors Transistors should only touch Poly or Diff Poly Contacts should NOT touch diffusion or diff contact Poly should NOT touch diffusion contact Pdiff Contact should not touch Ndiff contact FITNESS FUNCTION PENALIZES MAX_PENALTY FOR…

18. Incomplete designs – broken connections 10+penalty for broken connections + DRC Complete designs with DRC errors and/or Circuit simulation errors Penalty for “incorrect simulation” + DRC errors Errors in a Design : 2 FITNESS FUNCTION PENALIZES…

19. 11 Building Blocks

20. Encoding an Object A B 14 0 Cell limits Y 15 0 Cell limits X 5 0 Cell limits Stretch Factor 2 0 0-3 Orientation 11 11 1-15 Object Type B A VALUE PARAMETER

21. An Individual Y X Stretch Factor Orientation Object Type

22. Connections b/w Transistors terminal

23. Key MAGIC SPICE “ If you have some terminal that is not being influenced by any other terminal, we want to know how close it is to some terminal that can influence it. ”

24. An Influence Check Domain specific rules encouraging connectivity The labels must not be shorted Every input must influence at least one output Every output must be influenced by at least one input The gate of a transistor must be influenced by at least one input One terminal of the transistor must be influenced by an input Other terminal of the transistor must influence an output

25. Sample Cell Corresponding Graph

26. Results

27. Success 1

28. Success 2

29. Success 3

30. Evolving 1

31. Evolving 2

32. Evolving 3

33. Evolving 4-7 4 6 5 7

34. Evolving 8: Aha! Inverter

35. Evolving – Success 1

36. Limitations Does not always find the best solution – Is this acceptable? Presently unable to design more complex cells Alternative representation Starting from similar designs Speed – almost linear speedup [Mazumder]

37. References 1 T. Lengauer. Combinatorial Algorithms for Integrated Circuit Layout. K. Rasheed. GADO: A Genetic Algorithm for Continuous Design Optimization, PhD. Thesis. http://www.cs.uga.edu/~khaled P. Mazumder and E. M. Rudnick. Genetic Algorithms for VLSI Design, Layout & Test Automation. D. E. Goldberg. Genetic Algorithms in Search, Optimization and Machine Learning. J. Rabaey. Digital Integrated Circuits: A Design Perspective.

38. References 2 N. H. E. Weste, K. Eshragian. Principles of CMOS VLSI Design. C. Edwards . EDA Vendors Rethink Standard-Cell Libraries, Electronics Times, June 2000. D. Pietromonaco. Automating Cost-Effective Library Creation, Integrated System Design, November 2000. http://www.research.compaq.com/wrl/projects/ magic / http://bwrc.eecs.berkeley.edu/Classes/IcBook/ SPICE / http://ece.www.colorado.edu/~ecen4228/ spice /spice.htm

39. Merci Danke Sas efharisto Mahalo Merci Dhanyavaad Arigato Vandane Wneeweh Shukran