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An Evolutionary approach to Standard Cell Design: a proof of concept Anil Bahuman Artificial Intelligence Center University of Georgia July 2001
 
 
 
Research Goal Truth Table Layout with “minimum” area “ Schematic and layout are designed in parallel” Explore possibility of automating the design of simple logic standard cells by exploring design spaces not considered by human designers 1 0 1 0 0 1 Out In
Standard Cell Design ,[object Object],[object Object],[object Object],[object Object],[object Object],Standard cells are building blocks of frequently used logics employed in VLSI Design.  Examples include NAND, Full Adder, Latch and Inverter.  These libraries are typically designed by hand in a very costly and time consuming process.  One of the major challenges is the migration of standard cell layouts every time there is a change in the process.  There is a strong need for automation alternatives.
Design Example
A Transistor in MAGIC
Error tiles indicating DRC Errors
An Inverter in MAGIC Lambda, cell limits, labels, template, inputs, output, gate, terminals, wires, poly, contacts, 3I - 1O
SPICE simulation of the Inverter
Research Goal
Research Goal – Inverter Truth Table Layout with “minimum” area “ Schematic and layout are designed in parallel” 1 0 1 0 0 1 Out In
Why Is This Worth Our Efforts? ,[object Object],[object Object],[object Object],[object Object]
Architecture
architecture MAGIC  SPICE Modified GADO (DRC ERRORS , AREA) (CORRECTNESS) DESIGN ENGINE EVALUATOR DESIGN RULE CHECKER CIRCUIT SIMULATOR Fitness module (CIRCUIT FILE)
Errors in a Design : 1 ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],FITNESS FUNCTION PENALIZES MAX_PENALTY FOR…
[object Object],[object Object],[object Object],[object Object],Errors in a Design : 2 FITNESS FUNCTION PENALIZES…
11 Building Blocks
Encoding an Object A B 14 0 Cell limits Y 15 0 Cell limits X 5 0 Cell limits Stretch Factor 2 0 0-3 Orientation 11 11 1-15 Object Type B A VALUE PARAMETER
An Individual Y X Stretch Factor Orientation Object Type
Connections b/w Transistors terminal
Key ,[object Object],[object Object],“ If you have some terminal that is not being influenced by any other terminal, we want to know how close it is to some terminal that can influence it. ”
An Influence Check ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Sample Cell Corresponding Graph
Results
Success 1
Success 2
Success 3
Evolving 1
Evolving 2
Evolving 3
Evolving 4-7 4 6 5 7
Evolving 8: Aha! Inverter
Evolving – Success 1
Limitations ,[object Object],[object Object],[object Object],[object Object],[object Object]
References 1 ,[object Object],[object Object],[object Object],[object Object],[object Object]
References 2 ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Merci  Danke   Sas efharisto   Mahalo  Merci  Dhanyavaad  Arigato   Vandane  Wneeweh  Shukran

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Example of Automating Transistor-level Design