This document summarizes an article from the International Journal of Electronics and Communication Engineering & Technology about implementing a scalable queue manager on an FPGA. It discusses how traditional per-flow queue managers require a large number of queues that scales with the number of flows, consuming significant memory. The proposed architecture uses dynamic queue sharing to allocate a limited number of physical queues for active flows only. It can operate in per-flow or per-class modes depending on traffic conditions to reduce queue exhaustion. The algorithms were implemented on an FPGA and showed reductions in required memory and device utilization compared to only using dynamic queue sharing.