This document provides an overview of fault tree analysis including:
- Fault tree analysis models possible failure combinations using logic gates like AND and OR to relate events leading to an undesired top event.
- It involves defining the system, top event, tree structure, then exploring each branch in detail until all failure pathways are identified.
- Boolean algebra is used to evaluate the tree qualitatively by finding minimal cut sets, and quantitatively by calculating failure probabilities.
- An example fault tree is provided for a simple electric motor circuit to demonstrate the construction process and rules.