F21-LOGIC DESIGN Advanced lec-FOE-CMPN111 SP23.pptx

Dr. Ihab Talkhan
1
LOGIC DESIGN II
Credit Hour System
Computer Eng. Dept.

Dr. Ihab Talkhan
2
Cairo University
Faculty of Engineering
Computer Engineering Department
Logic Design II
Monday – SPRING 2023
Course Description:
An advanced course in digital circuit design, this course begins with a review of
switching algebra and combinational design, programmable logic devices, and
combinational circuits including encoders/decoders and
multiplexers/demultiplexers. Sequential circuits using latches, flip-flops, ROM and
RAM and also reviewed. Topics in sequential circuit design are treated, including
finite state machines, Mealy and Moore models, state diagrams and state tables,
optimization, asynchronous sequential circuits, and races and hazards. In
addition, implementation of sequential circuits with programmable logic devices is
discussed, as are topics in logic circuit testing and testable design.
Credit: This course consists of 2 Hour lecture per week
Text book:
• M.Morris Mano and Michael D. Ciletti, “Digital Design with an Introduction to
the Verilog HDL” , 5th edition, Dorling Kindersley (india) Pvt. Ltd, 2013
• M. Morris Mano, Michael D. Ciletti, “ Digital Design” , 5th edition, Prentice Hall,
2012
• Digital Fundamentals with VHDL by Thomas F Floyd, Prentice Hall, 2003

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Instructor(s): Dr. Ihab E. Talkhan
This course is designed to Let:
1. Students learn the electrical characteristics of CMOS and TTL logic
gates and should understand how these devices function in a typical
application circuit, including interfacing with other circuit elements.
2. Students learn how to design practical digital systems using standard
medium scale and large scale integrated circuits, including
programmable logic circuits.
3. Students learn how to use modern CAD tools including schematic
capture editors, simulations, and logic synthesis compilers based on
VHDL.
4. Students gain experience with a variety of standard digital memory
circuits and subsystems, and should understand their internal design
and their application in more complex systems.
5. Students gain experience with digital system testing techniques

Course contents:
Assignments
Title
#
Selected
problems from
the Text Books
Introduction. Overview of digital concepts
1
Review of basic Number systems, Boolean Algebra and combinational
logic design
2
Timing in combinational circuits, Loading, Noise Margins, Logic gate
Fanout, Timing hazard
3
Programmable logic: PLDs, FPGAs, etc.
4
MSI and VHDL implementations of building block components:
5
Decoders, MUXs, tri-state logic, Adders, etc.
Design examples using combinational components
6
Review of sequential logic elements and systems: flip-flops, counters and
shift-registers
7
Clocked synchronous state machines
8
Synchronous design using state machines
9
Practical timing considerations and designs using VHDL
10
Memory components (ROM, SRAM, DRAM)
11
Testability
12

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 Grading: 20 point (MID-Term - no make-ups)
for CR, 3 absence max.)
40 points Assignments/ Labs / Project (all
assignments from the text book, end of chapter
selected problems
+ FINAL out of 40
 Testing dates: to be announced later
 Final test date: refer to First term Schedule
 Assistant: to be announced later
 Office hours: to be announced later
 italkhan@aucegypt.edu
 italkhan@cu.edu.eg. currently not used

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Design Cycle

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The Packaging Sequence

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ASIC Design Flow

10
Memory & Programmable Logic

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Major Units
 For any system, there are three major units:
Central processing unit CPU
Memory unit
Input/Output unit
 In digital system, memory is a collection of cells capable of
storing binary information (permanent or temporary).
 It contains electronic circuits for storing and retrieving
information.
 It interacts with the CPU and input/output units.

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Memory types
Random Access Memory
RAM
Read Only Memory
ROM
• It is a programmable logic
devices PLDs, which are
integrated circuits with
internal logic gates
connected through
electronic fuses.
• Programming is done by
blowing these fuses to
obtain the desired logic
function.
• Accept new information for
storage to be available later
for use (write)
• Transfer stored information
out of memory (read)
• RAMs may range on size
from hundreds to billions of
bits.
• It is volatile

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Conventional
Symbol
Array Logic
Symbol

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Example of a PLD Chip

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History of Computational Fabrics
 Discrete devices : relays, transistors (1940s – 50s).
 Discrete logic gates (1950s – 60s).
 Integrated circuits (1960s – 70s).
 e.g. TTL packages : Data Book for 100’s of different parts.
 Gate Arrays (IBM 1970s).
 Transistors are pre-placed on the chip & Place and Route software puts the chip
together automatically – onlky program the interconnect (mask programming).
 Software Based Schemes (1970’s – present).
 Run instruction on a general purpose core.
 ASIC Design (1980’s to present).
 Turn Verilog/VHDL directly into layout using a library of standard cells.
 Effective for high-volume and efficient use of silicon area.
 Programmable Logic (1980’s to present).
 A chip that be reprogrammed after it has been fabricated.
 Examples: PALs EPROM, EEPROM, PLDs, FPGAs.
 Excellent support for mapping from Verilog/VHDL.

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TTL Logic Style (1970’s early 80’s)

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MOS Technology : The NMOS MOS
Switch

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PMOS: The Complementary Switch

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The CMOS Inverter

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Programming Technology
 To establish the programmable connections the following
technologies are used:
EPROM
EEPROM
FLASH

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EPROM
 used to create a wired –AND function. The transistor has two gates, a
select gate and a floating gate, charge can be accumulated and trapped on
the floating gate by a mechanism called avalanche injection or hot electron
injection. These transistors are referred to as FAMOS (Floating gate
Avalanche-injection MOS). Note that without a charge on the floating gate
the FAMOS acts as a normal n-channel transistor in that when a voltage is
applied to the gate, the transistor is turned on. EPROM cells provide a
mechanism to hold a programmed state, which is used in PLDs or CPLDs
to establish or not establish a connection. To erase the cell remove charge
from the floating gate by exposing the device to ultraviolet light. (typical
erasure time is about 35 minutes under high-intensity UV light.

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EEPROM
 E2PROM, used to create a wired AND-function. It consists of two
transistors (select & storage transistors). These transistors are referred to as
FLOTOX (Floating gate Tunnel Oxide transistors). It is similar to the
FAMOS except that the oxide region over the drain is considerably smaller,
less than 10 Ao (Angstroms) compared to 200 Ao for the FAMOS. This
allows charges to be accumulated and trapped on the floating gate by a
mechanism called Fowler-Nordheim tunneling. E2PROM cells require a
select transistor because when the floating gate does not hold a charge, the
threshold voltage of the FLOTOX transistor is negative.

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FLASH
 like E2PROM, FLASH cells consist of two transistors (select
& storage transistors). They create a wired AND function.
The storage Transistor is a FAMOS, so programming is
accomplished via hot electron injection. However the floating
gate is shared by an eraser transistor that take charge off it via
tunneling.

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RAM
 Random access from any random location.
 It stores information in groups of bits (called “words”.
 A word is a group of 1’s & 0’s (represents numbers,
instructions, alphanumeric characters, binary coded
information).
 Normally, a word is a multiples of 8 bits (1 byte) in length,
where 1 byte = 8 bits.
 Capacity of memory = total number of bytes.

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Communications between Memory &
Environment
 Communications between memory and environment is done
through:
In/Out lines
Address selection lines
Control lines

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Memory Unit Block Diagram
Memory Unit
2k words
n bits/word
n data-in lines
n data-out lines
K-address
lines
Read
Write
K-address = specify particular
word chosen
R/W Control = Direction of transfer
• Computer range from 210=1024 words (requiring address of 10-bits) to
232 (requiring 32 address bits)

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Units
 Kilo “K” = 210
 Mega “M” = 220
 Gega “G” = 230
 64 K = 216 (26 x 210 )
 2 M = 221
 4 G = 232

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Memory Address
Memory Content
Decimal
Binary
1101100101011100
0
1023
0000000000
1111111111
Content of 1024 x 16 Memory L 1K x 16bit
i.e. 10 address lines & 16-bit word
Note: 64K x 10 16 bits in address , 10-bits word
2k = m , m total number of words, K number of address bits (lines)

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Write & Read
 Write
Transfer binary address of desired word to address lines.
Transfer data bits that must be stored to data-in lines
Activate write-in
 Read
Transfer binary address to address lines.
Activate read-in

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Memory Chip Control
Select
Out
R/W
IN
Basic Cell
S
R

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Operation
Read/Write
Memory Select
None
X
0
Write
0
1
Read
1
1
Basic
Cell
OUT
IN
R/W
Select
m words of n-bits/word consists of n x m binary storage cells
R/W = 1 read path from F.F to output
0 In to F.F.

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Data-
IN
Data-
OUT
RAM
16 x 4
Address-
lines
Memory Select
R/W
Memory Chip Symbol

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3-State Buffer
 It exhibits three distinct states, two of the states are the logic 1
and logic 0 of conventional logic. The third state is the high-
impedance (Hi-Z) state.
 The high-impedance state behaves like an open circuit, i.e.
looking back into the logic circuit, we would find that the
output appears to be disconnected.

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IN OUT
ENABLE ) EN)
OUT
IN
EN
Hi-Z
0
1
X
0
1
0
1
1

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Properties of Memory
 Integrated circuit “RAM” may be either Static or Dynamic
RAM
Static RAM (SRAM) Dynamic RAM (DRAM)
• It consists of internal latches that
store the binary information.
• The stored information remain valid
as long as power is applied to the
RAM
• It stores the binary information
in the form of electric charges
on capacitors, the capacitors
are accessed inside the chip
by n-channel MOS transistors.

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• The stored charge on the
capacitors tends to discharge
with time, and the capacitors
must be periodically recharged
by refreshing the DRAM. This is
done by cycling through the
words every few milliseconds,
reading and rewriting them to
restore the decaying charge.
• It offers reduced power
consumption and larger storage
capacity in a single DRAM chip
RAM
Static RAM (SRAM) Dynamic RAM (DRAM)
• SRAM is easier to use and
has shorter read/write cycles.
• No refresh is required

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 Memory units that lose stored information when power is
turned-off are said to be Volatile.
 Both SRAM & DRAM are of this category, since the binary
cells needs external power to maitain the stored information.
 Magnetic disks, CDs as well as ROM are non-volatile
memories, as they retain their stored information after the
removal of power.

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Array of RAM Chips
 Combine a number of chips in an array to form the required
memory size.
 Capacity = number of words & number of bits/word
 increase in words  increase in address
 Usually input and output ports are combined, to reduce the
number of pins on the memory package.

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4 x 4 memory

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4 x 4 Memory
 It consists of 16 memory cells “MCs”.
 For each memory access, the address decoder decodes the address and
selects one of the rows.
 If RWS & CS are both equal to “1”  the new content will be written into
each cell of the row selected. Note that the output drivers are disabled to
allow the new data to be written-in
 If RWS = 0 & CS = 1  the data from the row selected will be passed
through the tri-state drivers to the IO pins.

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Design Flow Diagram
 Design description
 Synthesis
 Placement
 Routing
 Test Benches for design verification
Design flow diagram

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Design Constraints
 Time-to-market
 Cost
 Design Features
 Performance
 Manufacturing capabilities
Design constraints

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System Design Requirements
 Increasing Functionality
 Higher performance
 Lower cost
 Lower power consumption
 Smaller dimensions
· Need to create
highly integrated,
complex systems
with fewer IC
devices and less
printed-circuit-
board PCB area.

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Technologies available
 PCB technology
 Surface mounting Devices (SMD)
 Multi-chip Modules MCMS
 Custom Design
 Application Specific Integrated Circuit ASIC (SC, GA,
PLD, CPLD, FPGA)

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Standard Cell

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Gate-Arrays

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How to Define your Hardware
 Function description
 Algorithms
 Equation
 Symbols (schematic capture)
 Data from graphs
 Netlist
 Truth table
 Waveforms (timing diagrams)
 VHDL

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Future Integrated CAD

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Schematic Capture
(Small Designs)
 It provides a graphical view of the design
 It uses software tools that support schematic hierarchy
 Design modularity ( ‫قابلية‬
‫التجزؤ‬ )

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But Capturing Large designs is
difficult:
 Control logic must still be generated using traditional design
techniques
 Schematic is difficult to maintain
 Schematic capture environment are proprietary ( ‫إمتالكى‬
،
‫خاص‬ ), so a
designer who works in a schematic capture environment for one
project may not be able to reuse material when working on a new
project that requires the use of a new schematic capture environment
 The simulation environment supported by PLD schematic capture tool
may not fit with the system design environment, making design
verification difficult at best.

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Bottleneck with increasing complexity of
designs
 Electronic Design Automation (EDA) tools
 Accelerated time-to-market schedules

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Appropriate Design Methodologies
 Increase the efficiency of designers
 Facilitate capturing, understanding and
maintaining a design
 Not open to interpretation
 Open, not proprietary, standard accepted by
industry
 Allow designs to be ported from one EDA
environment to another, thus modules can be
packaged and reused
VHDL
&
Verilog
Languages
satisfy
These
requirements

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Appropriate Design Methodologies
(cont.)
 Support complex designs and hierarchy and
gate-level to system-level design
 May be used for description, simulation
and synthesis of logic circuits
 Support different design entries
 Supports multiple levels of design
description
VHDL
&
Verilog
Languages
satisfy
These
requirements

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Modern Methodologies
in design and test
 Semi-custom & Full-custom Application
Specific Integrated Circuit ASIC
 High-density Programmable Logic Devices
PLDs
 Complex High-density Programmable Logic
Devices CPLDs
 Field Programmable Gate Arrays FPGAs
 Hardware Description Language VHDL
 Very High Speed Integrated Circuit VHSIC
Hardware Description Language
500 to more
than 100,000
gates, thus
Boolean
equations or
gate-level
descriptions are
no longer
efficient to
quickly
complete a
design

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VHDL History
 VHDL ( a product of the VHSIC (Very High Speed
Integrated Circuit) program funded by the Department of
Defense (US government) in 1970s & 1980s) is well suited
for designing with programmable logic devices (it is one
language for design & simulation).
 It was endorsed by IEEE in 1986 in its attempt at
standardization.
 By December 1987 the IEEE 1076.1 standard for VHDL was
approved and a VHDL Language Reference Manual (LRM)
was published.

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VHDL properties
 it provides high-level language constructs that enable
designers to describe large circuits and bring products to
market rapidly.
 It supports the creation of design libraries for reuse in
subsequent designs.
 It is a standard language (IEEE standard 1076), thus it
provides portability of code between synthesis and simulation
tools as well as technology-independent design.

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VHDL properties (cont.)
 Reduction of a design description to lower-levels (such as
netlist), and it serves the needs of designers at any level
 It facilitates converting a design from programmable logic to
an ASIC implementation.

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VHDL Advantages
 Standard
 Government Support
 Industry Support
 Portability
 Modeling Capability (Power & Flexibility)
 Reusability
 Technology & Foundry independence
 Documentation
 New Design methodology

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Standard
 VHDL is an IEEE standard (such as graphic X-windows
standard, bus communication interface standard, and so on).
 It reduces confusion and makes interfaces between tools,
companies, and products easier.
 Any development to the standard would have better chances of
lasting longer and have less chance of becoming obsolete due
to incompatibility with others.

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Government Support
 VHDL is a result of the VHSIC program, so it is clear that the
US government supports the VHDL standard for electronic
procurement.

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Industry Support
 Companies use VHDL tools not only with regard to defense
contractors, but also for their commercial designs.

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Portability
 VHDL permits you to simulate the same design description
that you synthesized, simulating a several-thousand-gate
design description before synthesizing can save a considerable
amount of time & effort.
 VHDL is standard, design description can be taken from one
simulator to another, one synthesis tool to another, and one
platform to another, i.e. VHDL design descriptions can be
used in multiple projects.

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VHDL
CODE
Compiler
B
Compiler
A
Compiler
C
Custom
PCB ASIC
One design
Any Synthesis tool
Any vendor/device
VHDL Portability property
VHDL provides portability between compilers &
Device independent design

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Modeling Capability
(Power & Flexibility)
 It has powerful language constructs (code description of
complex control logic)
 It has multiple levels of design description for controlling
design implementation
 It supports design libraries & the creation of reusable
components
 It provides for design hierarchies to create modular designs

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Device-independent Design
 You can create a design without having to first choose a
device for implementation, with one design description you
can target many device architecture.
 It permits multiple styles of design description, i.e. it permits
several classes of design description.

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Device-independent Design
U1: xor2 port map(a(0),b(0),x(0)));
U2: xor2 port map(a(1),b(1),x(10);
U3: nor2 port map(x(0),x(1),aeqb);
aeqb  (a(0) XOR b(0)) NOR (a(1)
XOR b(1));
aeqb  `1` when a = b else `0`;
If a = b then aeqb  `1`;
Else aeqb  `0`;
End if;
Netlist Boolean equationst
Concurrent statements Sequential statements
2-bit Comparator

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Benchmarking Capabilities
 Device-independent design & portability allow you
benchmark a design using different architectures and different
synthesis tools.

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ASIC Migration
 The efficiency the VHDL generates allows your product to hit the market
quickly.
 When production volumes reach appropriate levels, VHDL facilitate the
development of an ASIC, sometimes the exact code used with the PLD can
be used with the ASIC.

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Quick time-to-market & Low Cost
 VHDL & programmable logic pair facilitate a speady design
process, as VHDL permits designs to be described quickly and
Programmable logic eliminates NRE expenses and facilitates
quick design iterations.
 VHDL & programmable logic combine as a powerful vehicle
to bring your products to market in record time.

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Design Tool Flow
 Synthesis Software
 Fitter (CPLD) or Place & Route (FPGA) routines
 Simulation Software
 Programmable Logic Primer

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Synthesis Software
 The inputs to the synthesis software are:
 The VHDL design source code.
 Synthesis directives.
 Device selection (required to perform device-
specific synthesis & optimization).
 The output of the synthesis software is:
 An architecture-specific netlist or set of equations

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Fitter (CPLD) or Place & Route (FPGA)
routines
 Inputs to these routines are the outputs from the synthesis
software.
 Outputs are information about resource utilization, static ,
point-to-point, timing analysis, a device programming file, and
a post-layout simulation model.

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Simulation Software
 The simulation model, along with a test bench or other
stimulus format, is used as input to the simulation software.
 Outputs are waveforms or data files.

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Programmable Logic Primer
 Texas Instruments TTL series 54/74 logic circuits are the
mainstay of digital logic design for implementing SSI & MSI
combinational & sequential logic (multiplexing, encoding,
decoding, selecting, registering, designing state machines &
other control logic).
 This type of implementation include discrete logic gates,
specific Boolean transfer functions, memory elements,
counters, shift registers and arithmetic circuits.
 A standard design flow is shown in the next figure.

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A standard design flow

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ASIC Design Flow

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History of Computational Fabrics
 Discrete devices : relays, transistors (1940s – 50s).
 Discrete logic gates (1950s – 60s).
 Integrated circuits (1960s – 70s).
 e.g. TTL packages : Data Book for 100’s of different parts.
 Gate Arrays (IBM 1970s).
 Transistors are pre-placed on the chip & Place and Route software puts the chip
together automatically – onlky program the interconnect (mask programming).
 Software Based Schemes (1970’s – present).
 Run instruction on a general purpose core.
 ASIC Design (1980’s to present).
 Turn Verilog/VHDL directly into layout using a library of standard cells.
 Effective for high-volume and efficient use of silicon area.
 Programmable Logic (1980’s to present).
 A chip that be reprogrammed after it has been fabricated.
 Examples: PALs EPROM, EEPROM, PLDs, FPGAs.
 Excellent support for mapping from Verilog/VHDL.

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TTL Logic Style (1970’s early 80’s)

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MOS Technology : The NMOS MOS
Switch

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PMOS: The Complementary Switch

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The CMOS Inverter

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Possible Function of Two Inputs

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Common Logic Gates

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Exclusive (N)OR Gate

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Generic CMOS Recipe

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Reconfigurable Logic
 Logic blocks
 To implement combinational and
sequential logic.
 Interconnect
 Wires to connect inputs and
outputs to logic blocks.
 I/O blocks
 Special logic blocks a periphery
of device for external
connections.

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Reconfigurable Logic (cont.)
 Key questions:
 How to make logic blocks
programmable? (after chip has
been fabbed!)
 What should the logic granularity
be?
 How to make the wires
programmable? (after chip has
been fabbed!)
 Specialized wiring structures for
local .vs. long distance routes?
 How many wires per logic block?

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What is Programmable
Logic Device
 Programmable Array Logic (PAL) devices are the simplest programmable
logic devices.
 It consists of an array of AND gates and an array of OR gates in which the
AND array if programmable and the OR array is fixed.
 Figure 5 illustrates the standard gate symbol for an 3-input AND gate and
the equivalent PAL logic diagram. (the single line extending from the AND
gate is used to represent several inputs, the vertical lines represent the
signals A,B & C, An asterisk represents a programmed connection between
an input signal A, B or C and an input of the AND gate.
 The programmed connections are made via EPROM cells or another
programming technology.

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Programmable Array Logic (PAL)
 Based on the fact that any
combinational logic can be
realized as a sum-of-products.
 PALs feature an array of AND-
OR gates with programmable
interconnect

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Conventional
Symbol
Array Logic
Symbol

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Example: (A network repeater with four
communication ports)
 Communication ports are A, B, C, & D
 A collision signal X must be asserted ( ‫)تؤكد‬ if more than one port’s carrier sense is active at a time.
 Signal X is to be synchronized to the transmit clock.
 A truth table is generated from to design specification.
 Using Boolean algebra or Karnaugh map, we can reduce the expression for X to six product terms.
& an expression for the complement of X can be reduced to four product terms.
 It is required to either minimize the number of device required or to minimize the number of levels
of logic in order to minimize the total propagation delay OR strike a balance between the two,
depending on the performance and cost requirements of the design.
Note that the expression X = AB + CD + BD + BC + AD + AC may be rewritten in NAND-NAND
form as:
 This design requires two 7400s and one 7430, for a total of two levels of logic.
 Finally to synchronize X to the transmit clock, a 7474 (D-flip-flop) is used.
 This design can be implemented in one of several different ways.
 
AC
.
AD
.
BC
.
BD
.
CD
.
AB
X 

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Full-Adder (Example 2)
 It is a combinational circuit that forms the arithmetic sum of three input bits.
Carry from the
previous lower
significant position

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)
( Y
X
Z
XY
C
Z
Y
X
S






Z
Y
X
XYZ
Z
Y
X
Z
Y
X
Z
Y
X
S







)
(
)
(
Y
X
Z
XY
Y
X
Y
X
Z
XY
YZ
XZ
XY
C









Outputs
Inputs
S
C
Z
Y
X
0
1
1
0
1
0
0
1
0
0
0
1
0
1
1
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
10
11
01
00
1
1
0
1
1
1
YZ
X
10
11
01
00
1
0
1
1
1
1
YZ
X

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Using Standard Cells to build a Full Adder

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Using Standard Cells to build a Full Adder

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Example (PAL 16L8 device): (PAL
architecture)
 The 16L8 is so named because there are 16 inputs into the AND array, and
8 outputs, the L is for logic array.
 Eight of the inputs to the array are dedicated device inputs
 Another eight are from I/O pins.
 If three-state inverter associated with an I/O pin is enabled, then the input
to the logic array is actually a feedback associated with an OR gate, note
that the feedback is inverted, i.e. the input signal is from an inverting
buffer driven by an OR gate. If the three-state inverter is disabled then the
I/O pin is working as an input.
 There are 64 AND gates, each one can be used to create a product of any of
the 16 inputs or there complements.
 The 8 OR gates are fixed, each sums seven products and the remaining
eight product term are used for enables of the Three-state inverting buffers.

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Other examples
 The PAL 16R8 device which provides registers.
 The 16R6 includes six registers leaving two combinational output
structures with individual three-state control.
 The 16R4 is a compromise between the 16L8 & 16R8 with four registered
and four combinational output structures.

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______ __ _ ___
Example of a PLD Chip

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Designing with Programmable Logic:
 Back to example (1) Network repeater, because signal X must be
registered, The PAL 16R8 or 16R6 or 16R4 are used. Note that four 14 pin
devices were replaced by only 20-pin DIP (dual in-line package), and the
design used only a portion of the 16R8 device.

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Design Specifications
Design Description
Design Software
Fuse map

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Advantage of
Programmable Logic
 Fewer devices are used, 20 pin DIP (dual in-line package).
 One PAL could easily replace 10 or more TTL devices, which makes PAL
implementation more cost-effective.
 Saves valuable board spaces, power, debug time.
 Increases performance and design security.
 Integration increases design reliability because there are fewer dependencies on the
interconnections of devices.
 Integration increase performance by reducing the number of I/O delays and levels
of logic.
 Flexibility.
 Pal allows you to use design tools that help automate the process, as all you need is
to produce aone design description, leaving the logic synthesis and optimization
software to determine an adequate implementation (the design description can be
captured by VHDL and Verilog).

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Simple PLDs “22V10”
 Popular industry-standard PLDs:
 16V8
 20G10
 20RA10
 22V10 

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The 22V10
(V for variable, 22 inputs , 10 outputs)
 It consists of programmable macro-cell and a variable product-
term distribution. Each macro-cell may be individually
configured by programming the state of configuration bits.
Configuration bits allow a macro-cell input (sum of products)
to either be registered or pass directly to the output buffer. The
polarity of the macro-cell output is also selectable, either the
true or the complement of an expression may be used.

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Table: 22V10 macro-cell configuration
table
Description
C0
C1
Registered / active
low
0
0
Registered / active
high
1
0
Combinational /
active low
0
1
Combinational /
active high
1
1

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Inside the 22v10
“Macrocell” Block

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The 22V10 (cont.)
 The output polarity selection of the macro-cell enables
software to perform logic optimization on an expression and
its complement and to select the one that requires the fewest
logic resources. Note that the architects of the 22V10 varies
the product terms per OR gate from 8 to 16, the top & bottom
macro-cells are allocated 8 product terms, the middle macro-
cells are allocated 16 product terms, and the others are
allocated 10,12 or 14 depending on location. The 22V10 does
allocate 16 product terms to every macro-cell as doing so
would increase the cost to manufacture the device, many
applications don’t require more product terms.

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Timing Parameters
 The following are sample data-sheet parameters for a 22V10:
 Propagation delay tPD (max. 4 ns), defined as the amount of time it takes for
a combinational output to be valid after inputs are asserted at the device
pins.
 Setup time ts (min. 2.5 ns), defined as the amount of time the input to a flip-
flop must be stable before the active edge of the clock is applied to the
clock pin.
 Hold time tH (min. 0), defined as the amount of time for which the input to
the flip-flop must be held stable after the clock.
 Clock-to-output delay tCO (max. 3.5 ns), defined as the amount of time
after which the clock input is asserted at the device pin that the output
becomes valid at another device pin.
 Clock-to-output delay through the logic array tCO2 (max. 7 ns), defined as
the clock to output delay that does not route directly from a register to its
associated output pin, rather it represents the clock to output delay for a
signal that is fed back from the register through the logic array, through a
macro-cell configured in combinational mode, and to a device pin.

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Timing Parameters (cont.)
 System clock to system clock delay tSCS (max. 5.5 ns), (used
to determine the maximum frequency of operation), where:
it indicates the minimum clock period if register-to-register
operation is required, and accounts of the amount of time from
when the clock is asserted at the registers until the output of
one register is valid at the input of another register.

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Case Study
 It is required to design a 3-bit synchronous counter with an enable.
 The design has two additional outputs:
 One that is asserted when the present count is greater than three
 The second is asserted when the count is equal to six.
 PS ≡ Present State , NS ≡ Next State.
 Two inputs = clock & enable “e”, Five outputs = a, b, c, x &y
 Assume that all macro-cells are configured for active high logic, then -
output for each flip-flop must be multiplexed to the inverting output buffer.
This allows positive-logic implementation for A, B, and C (Q2, Q1 and Q0).
 Signal A, B, & C are the D-inputs to the flip-flops associated with output
signals a, b, & c.

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F.F.
Next
Present
Y
X
D0
D1
D2
Q0
Q1
Q2
E
Q0
Q1
Q2
0
1
2
3
4
5
6
7
0
0
0
0
0
0
1
0
0
0
0
0
1
1
1
1
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
0
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
Counter
>
E
Enable
Clear Q2 Q1 Q0
Enable = 0 no
change
= 1 count
D Flip-Flop Excitation Table
D
Q(t+1)
Q(t)
0
1
0
1
0
1
0
1
0
0
1
1
Three states 3 Flip-Flops, we
will use D F.F. as an example
Equivalent
to Q2
2
1
0 Q
Q
Q
Y 

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1
0
1
0
0
1
1
Q
Q
Q
Q
Q
Q
D




10
11
01
00
1
1
0
1
1
1
0
0 Q
D 
10
11
01
00
1
1
0
1
1
1
Q1Q0
Q2
 
0
1
2
0
1
2
0
1
2
0
1
2
0
1
2
0
1
2
0
2
1
2
2
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
D










10
11
01
00
1
0
1
1
1
1
Q1Q0
Q2
Q1Q0
Q2

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Q
2
Q
1
Q
0
C
0
C
1
C
2
C
3
E
D
1
D
0
D
2
carr
y
3-bit up-counter
Half-Adder

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Case Study (cont.)
 Notice that output x does not require any logic implementation as it is
equivalent to “a” (Q2).
 Signal y requires one product term.
 Note that based on the timing parameters mentioned before:
 Signal e is the only input to the device that has a setup time requirement, it
must be valid and stable at least 2.5 ns before the clock is asserted at the
pin.
 Outputs a, b, c, and x are valid at the output pins 3.5 ns (tOC) after the clock
input transitions.
 Output y is valid at its output pin 7 ns (toc2) after the clock input transitions
(more time is required for y to be valid because the outputs of the counter
must be decoded to produce it, and this decoding causes an additional delay
of 4 ns over tCO).

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Case Study (cont.)
 The maximum frequency is the reciprocal of tSCS 5.5 ns, i.e.
fmax = 180 MHz, this is a typical value, but it is not valid for
this case as output y takes 7 ns to propagate to an output pin.
Thus if the circuit were clocked at 180 Mhz, output y would
never be valid. This circuit could be clocked at the rate of the
reciprocal of 7 ns (143 MHz).

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Complex PLDs (CPLDs)
 Users create logic interconnections by programming
EPROM or EEPROM to form wide fan-in gates.
 Higher level of integration to improve system performance
 Uses less board space
 Improve reliability
 Reduce cost
 CPLD contains multiple logic blocks, each similar to a small
PLD like 22V10
 The logic blocks communicate with one another using
signals routed via a programmable interconnect (PI).

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Typical CPLD Architecture
 Functional Blocks contains a PLD AND-array that feeds its
macrocell.
 A macrocell includes an OR gate to complete AND-OR logic.
 Global Universal Interconnect Mechanisms (UIM) that reaches
all FBs on the chip.
AND
array
AND
array
AND
array
AND
array
MC
UIM
FB
I/O

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Example of CPLD Chip

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Programmable Interconnects
Allows any signal in the PI to route
To any logic block. Each term in the
PI is represented by a vertical wire
and is assigned as an input (through
a sense amp) to a given logic block, so
there is one PI term for each input to
a logic block.
An output from the logic block can
connect to one of the PI terms
through a memory element.
Device inputs can connect to the PI
terms as well.
There is one multiplexer for each
input to a logic block.
Signals in the PI are connected to the
inputs of a number of multiplexers for
each logic block.
The selection lines of these
multiplexers are programmed to
allow one input for each multiplexer
to propagate into a logic block.
 Wide multiplexers increase die area
and may reduce performance
Programmable Interconnects
Array-based Interconnects Multiplexer-based Interconnects

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 I/O cells are sometimes considered to be part of a logic
block, but in our case we will consider these to be separate.
 There is little differences between the product-term arrays of
the different CPLDs, the size of the array is important
because it identifies the average number of product terms
per macrocell and maximum number of product terms per
logic block.
 Different CPLD vendors have approached product-term
distribution with different schemes, the MAX family
(“family” meaning several devices with the same
architecture) of CPLDs [ Altera Cooperation & Cypress
Semiconductors]

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Different CPLDs Families
CPLDs Families
Altera Family
Cypress Semiconductor
Family
Advanced Micro Devices
MAX5000, AX7000…
• Rather than using the
variable product-term
distribution scheme of
the 22V10 (which
allocates a fixed but
varied number of
product terms,
8,10,12,14 or 16 per
macrocell).
MAX340,FLASH370,
FLASH370
• each macrocell is
allocated from zero
to 16 product term,
depending on the
requirements of the
logic expression
implemented at a
given macro-cell.
The MACH
• It allows product terms to
be steered in groups of four
product terms and used in
another macrocell without
an additional delay.
• For each group of
macrocells that must be
steered, one macrocell is
left unusable.
• This product term
distribution scheme does
not provide product term
sharing.

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Altera Family (cont.)
• The MAX family allocates four
product terms (product term
steering) per macro-cell while
allowing several expander product
terms to be allocated individually
to any maco-cell or macro-cells.
• With expander product terms, the
additional product terms are
allocated only to those macrocells
that can make use of them
(Product-Term-Sharing).
• An additional delay is incurred for
signals that use the expander
product terms, as the output must
pass through the logic array
before propagating to a macro-
cell.

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The Product-Term Distribution
Schemes Provides
 Flexibility for the designer, but the designer should
understand how logic resources may be used and the
trade-offs among architectures.
 Flexibility for software algorithms that will
ultimately choose how to use logic resources

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 CPLDs include macrocells that provide flip-flops &
polarity control, it offers more configurability than
the 22V10 PLD. Many can include flip-flops that
can be configured as D- or T-type operation.
 CPLDs often have I/O macrocells (a macrocell
associated with an I/O), input macrocells
(associated with an input pin), and buried
macrocells (similar to an I/O macrocell except that
its output cannot propagate directly to an I/O, rather
its output is fed back to the PI). Note that 22V10
has only an I/O macrocells.

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MAX340
 There are serveral inputs to this macrocell:
 The sum-of-products input is used as one input to the XOR gate.
 The second input to the XOR is an individual product term.
 The XOR gate can be used
 In arithmetic expressions (comparators) or
 To complement the sum of products expression. Or
 To serve the same function as the output polarity multiplexer found in
22V10
 To configure a flip-flop for T- JK-, SR-type operation.
 The Preset & Clear are individual NAND terms.
 The clock can be either the system clock or an internally generated (product-term)
clock. Knowing that the system clock provides the best performance while the
generated clock provides flexibility.
 The output of the macrocell can be configured as registered or combinational.
 This architecture provides both local feedback (i.e. the macrocell feedback does
not use the PI and is not available to other logic blocks) and global feedback
through the PI. The disadvantage of having local feedback is a more complicated
timing model and redundant resources.
 Buried macrocells for this family are identical to the I/O macrocells except that
their outputs are used only as feedback and do not drive I/O cells.

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 I/O cells are used to drive a signal off the device, depending on the state
of the output enable and to provide a data path for incoming signals.
With some architectures, it might contain switch matrices or output
routing pools. The advantage to this scheme is flexibility in determining
where logic can be placed in a logic blockin relation to where the I/O
cell is located. The disadvantage is an incremental delay associated with
the performance routing structure and the increased die size.
 The timing specifications for CPLDs are the same for those of a 22V10.
(propagation delay, setup, clock-to-output, register to register times).
 Postdesign implementation timing information is generally more
predictable with CPLDs than with FPGAs, it is an advantage that prior to
beginning a design, the performance of that design can be estimated with
good precision.

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Introduction to Field Programmable
Logic Devices
 Introduction
 Types of FPLDs
 Programming Technologies
 Logic Cell Architecture
 Routing Architecture
 Design Process

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Introduction
 Device rating for different device technologies
Speed
Density
Cost
Development time
Prototype & Simulation time
Manufacturing time
Future Modifications
Inventory Risk

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Technology Comparison
Custom Logic
Discrete Logic
FPLD
Requirement
■
□
■
Speed
■
□
■
Density
■
□
■
Cost
□
◘
■
Development
□
□
■
Prototype & Simulation
□
◘
■
Manufacturing
□
◘
■
Future
□
■
■
Inventory
■
□
■
Development tool
■ Very effective ◘ Adequate □ Poor

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12:26
‫م‬ 166
Dr. Ihab Talkhan
VHDL Course
Field Programmable Gate Array
(FPGA)
 FPGA is an array of logic cells that communicate with one
another & with I/O via wires within routing channels.
 Note that in semi-custom gate array Gate-Arrays the routing
is customized, without programmable elements, while in an
FPGA, existing wire resources that run in horizontal &
vertical columns (routing channels) are connected via
programmable elements.
 Logic cells have less functionality than the combined
product terms and macro-cells of CPLD, but large functions
can be created by cascading logic cells.

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Dr. Ihab Talkhan
VHDL Course
Types of FPLDs
 Commercial FPLD use different programming technologies,
different logic cell architectures and different structures of
their routing architectures.
 If programming technology and device architecture are
combined, three major categories of FPLDs are distinguished
Static RAM Field Programmable Logic Arrays, or SRAM
FPGAs
Complex Programmable Logic Device CPLDs.
Antifuse FPGAs

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12:26
‫م‬ 168
Dr. Ihab Talkhan
VHDL Course
Logic
Cell
I/O
Block
Interconn
ect
resources

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Dr. Ihab Talkhan
VHDL Course
Architecting an FPGA
 Performance, The ability for real system designs to operate at
increasingly higher frequencies.
 Density & capacity, the ability to increase integration, to place
more & more in a chip and to use all available gates within the
FPGA, thereby providing cost effective solution.
 Ease of use, the ability for system designers to bring their
products to market quickly (easy-to-use software tools for logic
synthesis, place & route,..).
 In-system programmability & in-circuit re-programmability

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Dr. Ihab Talkhan
VHDL Course
 Presently, there are two technologies of choice for use in
developing FPGAs
SRAM
Antifuse
 SRAM technology is presently used by Altera, Lucent
Technologies, Atmel, Xilinx.
 Antifues technology is presently used by Actel, Cypress,
Quicklogic, and Xilinx.
 Once a technology has been selected, it influences the choice of
routing architectures (as the physical dimensions of an SRAM
cell are an order of magnitude larger than those of an antifuse
element), which in turn influences the design of the logic cells.

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12:26
‫م‬ 173
Dr. Ihab Talkhan
VHDL Course
Static RAM FPGAs
 SRAM FPGAs implement logic as lookup tables made from
memory cells with function inputs controlling the address line.
 One or more LUTs, combined with flip-flops, form a
configurable logic block (CLB).
 CLBs are arranged in a two dimensional array with
interconnect segments in channels.

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12:26
‫م‬ 174
Dr. Ihab Talkhan
VHDL Course
Typical SRAM FPGA Architecture

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12:26
‫م‬ 175
Dr. Ihab Talkhan
VHDL Course
Programming Technology
 FPLD is programmed using electrically programmable
switches.
 The properties of these programmable switches, such as size,
volatility, process technology, on-resistance, and capacitance
determine the major features of an FPLD architecture.

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12:26
‫م‬ 176
Dr. Ihab Talkhan
VHDL Course
SRAM Programming Technology
 Uses SRAM cells to configure logic and control interconnections and paths
for signal routing.
 The configuration is done by controlling pass gate or multiplexers.
 Reprogrammable.
 Volatile.
 Large Area, at least 5 transistors are needed to implement SRAM cell.
 Uses standard integrated circuit process technology.
 External permanent memory required to provide the programming
bitstream at power-up time
MUX
4 x 1
Bit 0
Bit 1
SRAM
Cell
Pass
Gate

17/02/2023
12:26
‫م‬ 177
Dr. Ihab Talkhan
VHDL Course
Floating Gate Programming Technology
 Uses the technology erasable EPROM and electrically erasable EEPROM
devices.
 The unprogrammed switch is used to pull down a “bit-line” when the
“word –line” is set to high.
 It can be used to implement a wired-AND style of logic and routing.
 No external permanent memory is needed at power on.
 Reconfigurability not as fast as SRAM technology devices.
 Require extra processing steps over an ordinarily CMOS process.
 High on-resistance of EPROM transistor.
 High static power due to pull-up resistor used.

17/02/2023
12:26
‫م‬ 178
Dr. Ihab Talkhan
VHDL Course
Floating Gate Programming Technology
(cont.)

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12:26
‫م‬ 179
Dr. Ihab Talkhan
VHDL Course
Antifuse Programming Technology
 It irreversibly changes from high resistance to low resistance
when programmed.
 Relatively low on-resistance “100-600 Ohms”.
 Small size
 Programming requires extra circuitry to provide the high
voltage & relatively high current “5 mA” or more.

17/02/2023
12:26
‫م‬ 180
Dr. Ihab Talkhan
VHDL Course
Static RAM SRAM
An Amorphous-Silicon Antifuse
 SRAM cells are used to control
the state of pass transistors,
which can establish connections
between horizontal and vertical
wires. (the source to drain of
such a pass transistor is about
1000 ohm)
 SRAM cells are used to drive
the select inputs of multiplexers
that are used to choose from
one of several signals to route
on a given wire source.
 In amorphous (uncrystallized)
silicon based FPGA, the two
layers of metal are separated by
amorphous silicon, which
provides electrical insulation.
 A programming pulse of 10V to
12V with a necessary duration
can be applied across the via,
causing the top and bottom
layers of metal to penetrate the
amorphous silicon, creating a
bi-directional conductive link.
(with a resistance about 50
ohm)

17/02/2023
12:26
‫م‬ 181
Dr. Ihab Talkhan
VHDL Course
Static RAM SRAM
 An SRAM memory cell
consists of five transistors, two
for each of the two inverters
making up the latch and one
addressing (used to select the
memory cell for programming)
 An SRAM is programmable.
 SRAM cells are volatile, i.e. the
states of the memory cells are
lost when power is not applied,
SRAM-based FPGAs must be
programmed (usually from a
serial EPROM) each time the
circuit is powered on.
 Once programmed, an antifuse
element cannot be erased or
reprogrammed.
 Each antifuse element is
isolated by with pass transistors
so that other elements are not
inadvertently programmed,
these programming transistors,
constitute the programming
circuitry overhead.

17/02/2023
12:26
‫م‬ 182
Dr. Ihab Talkhan
VHDL Course
Static RAM SRAM
 The programming circuitry
for SRAM elements must
include the addressing and
data registers
(programming circuitry
overhead).
 Programmable elements are
strategically placed to
provide a trade-off between
routability, density and
performance.
 Actel FPGA products make use of an
Oxide-nitride-oxide (ONO) antifuse,
which consists of three layers : The
top, conductor made of polysilicon
(electrically connected to one layer of
metal), the middle, has an oxide-
nitride-oxide chemical composition
and is an insulator, the bottom, is a
conductive layer of negatively doped
diffusion. (300 ohm, link resistance)
 Because antifuse elements can be
placed very densely, FPGAs that use
this technology have flexibility
routing architectures, which allow the
electrical connection of wires at
nearly every intersection.

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Dr. Ihab Talkhan
VHDL Course
 Antifuse FPGAs are used when dealing with FPGAs that have routing
structures with many wires and many programmable connections, i.e.
smaller logic cells with more inputs and outputs relative to the number of
gates in the logic cell.
 FPGAs that have routing structures with fewer wires and programmbale
interconnections tend to have larger logic cells with fewer inputs and
outputs relative to the number of gates in the logic cell, SRAM FPGAs.
 Timing cannot be predicted easily for any but the simplest of dsigns
implemented in FPGAs. Signal propagation delays are functions of the
number of cascaded logic cells, the signal path in the logic cells, the
number of programmable interconnects through which the signal
propagates (as well as technology used, antifuse or SRAM), fan-out, and
I/O cell delays.

17/02/2023
12:26
‫م‬ 184
Dr. Ihab Talkhan
VHDL Course
Comparison of Programming
Technologies

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12:26
‫م‬ 185
Dr. Ihab Talkhan
VHDL Course
Technological & Operational
Differences Between the
Programmable Devices
Type Technology Switch Reprogram-
able ?
Volatile
?
Leading
Company
FPGA CMOS SRAM In-circuit Yes Xilinx
PLD
/CPL
D
CMOS EPROM
EEPRO
M
Out-of-circuit
In-circuit
No Altera
FPGA CMOS Antifuse No No Actel

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12:26
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Dr. Ihab Talkhan
VHDL Course
Xilinx (Example)

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12:26
‫م‬ 187
Dr. Ihab Talkhan
VHDL Course
Altera (Example)

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12:26
‫م‬ 188
Dr. Ihab Talkhan
VHDL Course
Actel (Example)

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