1. Optimized power
and speed of fir
filter using Mac
Unit

2. Under guidance of-
Dr. Richa Verma
By- Divyanshi Trivedi (74)
Kritika Srivastava (83)
Shikha Prajapati (99)
Shilpa Poddar (119)

3. Aimof Project
The main objective of our work is
optimization of multiplier and adder design
to produce more efficient solutions of FIR
filter. Specifically optimizing the internal
algorithm and architecture of multipliers
and adders. The objective of the work is
using new architectures or algorithms to
optimize power, speed and area and design
a mac unit based efficient fir filter.

4. FIR FILTER
FIR filter is implemented as a series of multiply and
accumulate operations on a programmable Digital Signal
Processor(DSP).

5. Direct Form FIR Filter

6. FIR Filter with Transposed Structure
A variation of the direct FIR model is called
the transposed FIR filter. It can be
constructed from the direct form FIR filter by
Exchanging the input and output
Inverting the direction of signal flow
Substituting an adder by a fork, and vice
versa

7. FIR Filter in the Transposed Structure

8. MAC UNIT
MULTIPLY-ACCUMULATOR UNIT
A conventional MAC unit consists of
multiplier and an accumulator that
contains the sum of the previous
consecutive products. A variety of
approaches to the implementation of the
multiplication and addition portions of
the MAC function are possible.

9. STRUCTURE OF MAC UNIT

10. ADDER
Addition is a fundamental operation in most digital
circuits
A combinational circuit that adds two bits is called a
half adder
A full adder is one that adds three bits, the third
produced from a previous addition operation

11. Carry ripple adder:
A ripple carry adder is a digital circuit that produces the
arithmetic sum of two binary numbers. It can be constructed
with full adders connected in cascaded, with the carry output
from each full adder connected to the carry input of the next
full adder in the chain.

12. Carry look ahead adder:
The carry lookahead adder (CLA) solves the carry delay problem by
calculating the carry signals in advance, based on the input signals. It is
based on the fact that a carry signal will be generatedin two cases:
 (1) when both bits 𝑎𝑖 and 𝑏𝑖are 1.
 (2) when one of the two bits is 1 and the carry-in is 1.

13. Carry select adder
The carry-select adder is simple but rather fast The carry-select adder
generally consists of two ripple carry adders and a multiplexer. Adding two
n-bit numbers with a carry-select adder is done with two adders (therefore
two ripple carry adders) in order to perform the calculation twice.

14. Carry skip adder
The carry-skip adder generates the output signals. This is
based on generate and propagation of signals. The block
diagram represents the signals and propagation of them.

15. Comparisons among carry ripple
carry look ahead and carry select
Parameters
Carry Ripple
Adder
Carry Look
Ahead Adder
Carry Select
Adder
Computational Delay 13.829ns 12.993ns 10.911ns
Levels of Logic 11 10 8
Power consumed 17mW 18mW 16mW

16. Comparisons between carry
skip and carry select
Parameters Carry select Adder Carry Skip Adder
Computational Delay
20.782ns 23.170
Levels of Logic
17 16
Power consumed
25mW 43mW

17. MULTIPLIER
Three stages in the multiplier architecture
1. Generation of partial products
2. Accumulation of partial product
3. Final addition

18. Array multiplier:
An array multiplier is a multipication method in which an array of
identical cell generates new partial products and accumulation of it at
a same time. Result from the adder can be latched at each level and
used as a input for next level adder circuit. An array multiplier is
nothing just a bit wise multiplication.

19. Conventional Wallace multiplier
C. S. Wallace suggested a fast multiplier during 1964 with
the combination of half adders and full adders.

20. ModifiedWallacemultiplier
It is an efficient hardware implementation of
a digital circuit that multiplies two integers.
It is a modification to the second phase
reduction method used in the conventional
Wallace multipliers, in which number of the
half adders is greatly reduced.

21. Wallacemultiplier
1)The partial product array is generates and it is
converted in the form of an inverted pyramid array.
2) Array is divided into group of three rows each

22.  Full adders are used to
add 3 bit
 Single bit and two bits
are forwarded to next
stage as it is
No of rows in per stages
ri+1 = 2[ri /3] + ri mod 3
If ri mod 3=0 then half
adder used
Modified Wallace 9-bit by 9-bit Reduction

23. Comparisons Among Different Multipliers
Parameters
Array
Multiplier
Conventiona
l Wallace
Multiplier
Modified
Wallace
Multiplier
Computational Delay 25.33ns 22.024ns 19.147ns
Levels of Logic 19 15 13
Power consumed 19mW 45mW 18mW

24. Conventional fir filter
DIRECT FORM FIR FILTER
TRANSPOSED FIR FILTER

25. 4 tap Direct Form fir filter

26. 4 tap transpose FIR filter

27. Comparisons between
conventional FIR filter
Parameters Direct form FIR
filter
Transpose form FIR
filter
Power consumed 84mw 81mw
Max computational delay 15.107ns 13.922ns
Levels of Logic 11 11

28. Mac unit based fir filter

29. Mac BASED FIR FILTER USING

30. Mac based Fir using

31. Mac based Fir Filter using

32. Comparisons AMONG MAC based
FIR filter
Parameters MAC
conventional FIR
filter
MAC skip FIR
filter
MAC select FIR
filter
Power consumed
116mW 85mW 78mW
Max
computational
delay
4.57ns 11.219ns 9.828ns
Levels of Logic
19 9 10

33. Comparisons Between Conventional FIR
And Mac Based FIR Filter
Parameters
Transpose form FIR
filter
MAC select FIR filter
Power consumed 81mw 78mW
Max computational
delay
13.922ns 9.828ns
Levels of Logic 11 10

34. THANK YOU…!!