IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
This document summarizes a research paper that proposes a technique called reconfigurable built-in self test (RBIST) to detect and correct faults in field programmable gate arrays (FPGAs). The RBIST approach uses the partial reconfiguration capability of FPGAs to dynamically reconfigure logic blocks and implement a self-test controller for fault detection. The self-test controller coordinates test pattern generation, response verification, and identification of faults. The technique was implemented on a Xilinx FPGA board to demonstrate fault detection and correction without disrupting the normal operation of other logic blocks.
An application specific reconfigurable architecture for fault testing and dia...eSAT Journals
This document discusses application-specific reconfigurable architectures for fault testing and diagnosis in FPGAs. It provides an overview of different types of faults that can occur in FPGAs at runtime, including logical faults, interconnect faults, and delay faults. It then reviews several previous works that proposed various techniques for application-independent and application-dependent fault diagnosis in FPGAs, focusing on methods for detecting and locating logical faults and interconnect faults. The goal is to remove faults at the application level to improve FPGA performance and reliability.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
The document discusses a two-day training on design for testability using Synopsys' DFT Compiler and TetraMAX tools. Day 1 covers basic DFT concepts and techniques including scan path insertion and memory wrappers using DFT Compiler. Day 2 focuses on TetraMAX for fault simulation, modeling memories, and debugging problems.
The document proposes a modified 5-stage pipelined MIPS processor architecture to reduce dynamic power consumption. Unnecessary transitions during unused pipeline stages consume extra power. The proposed architecture reduces these transitions by bypassing unused stages, such as bypassing the memory access stage for arithmetic instructions. It includes instruction and data memory, register file with dual write ports, datapath, control unit, forwarding unit, and hazard detection. Verilog modeling and synthesis shows the proposed design operates at 193.98MHz with 26.5% lower power compared to a single write-port pipeline.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Multinode Cooperative Communications with Generalized Combining Schemesakrambedoui
This document summarizes a graduation project presentation on cooperative communications using multiple relay nodes. It describes the system model involving a source, destination, and multiple relays. An incremental relaying protocol is proposed where relays transmit in successive phases if the combined signal strength from previous relays falls below a threshold. Analytical expressions for symbol error rate are developed for both maximal ratio combining and generalized selection combining schemes. Results show symbol error rate decreases as the number of relays increases. The average number of time slots needed per transmission is also analyzed. Finally, joint adaptive modulation and incremental relaying is proposed to further improve performance.
The document discusses multi-programming, time-sharing, and real-time systems. It describes how interrupts are handled by the supervisor process and how they can be masked. It also explains how multiple processes can be run concurrently by switching between them when they enter waiting states, with the scheduler selecting the next ready process to run based on priorities. Job classes are divided into CPU-bound and I/O-bound processes, and spooling is used to share sequential peripherals by queuing output.
This document summarizes a research paper that proposes a technique called reconfigurable built-in self test (RBIST) to detect and correct faults in field programmable gate arrays (FPGAs). The RBIST approach uses the partial reconfiguration capability of FPGAs to dynamically reconfigure logic blocks and implement a self-test controller for fault detection. The self-test controller coordinates test pattern generation, response verification, and identification of faults. The technique was implemented on a Xilinx FPGA board to demonstrate fault detection and correction without disrupting the normal operation of other logic blocks.
An application specific reconfigurable architecture for fault testing and dia...eSAT Journals
This document discusses application-specific reconfigurable architectures for fault testing and diagnosis in FPGAs. It provides an overview of different types of faults that can occur in FPGAs at runtime, including logical faults, interconnect faults, and delay faults. It then reviews several previous works that proposed various techniques for application-independent and application-dependent fault diagnosis in FPGAs, focusing on methods for detecting and locating logical faults and interconnect faults. The goal is to remove faults at the application level to improve FPGA performance and reliability.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
The document discusses a two-day training on design for testability using Synopsys' DFT Compiler and TetraMAX tools. Day 1 covers basic DFT concepts and techniques including scan path insertion and memory wrappers using DFT Compiler. Day 2 focuses on TetraMAX for fault simulation, modeling memories, and debugging problems.
The document proposes a modified 5-stage pipelined MIPS processor architecture to reduce dynamic power consumption. Unnecessary transitions during unused pipeline stages consume extra power. The proposed architecture reduces these transitions by bypassing unused stages, such as bypassing the memory access stage for arithmetic instructions. It includes instruction and data memory, register file with dual write ports, datapath, control unit, forwarding unit, and hazard detection. Verilog modeling and synthesis shows the proposed design operates at 193.98MHz with 26.5% lower power compared to a single write-port pipeline.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Multinode Cooperative Communications with Generalized Combining Schemesakrambedoui
This document summarizes a graduation project presentation on cooperative communications using multiple relay nodes. It describes the system model involving a source, destination, and multiple relays. An incremental relaying protocol is proposed where relays transmit in successive phases if the combined signal strength from previous relays falls below a threshold. Analytical expressions for symbol error rate are developed for both maximal ratio combining and generalized selection combining schemes. Results show symbol error rate decreases as the number of relays increases. The average number of time slots needed per transmission is also analyzed. Finally, joint adaptive modulation and incremental relaying is proposed to further improve performance.
The document discusses multi-programming, time-sharing, and real-time systems. It describes how interrupts are handled by the supervisor process and how they can be masked. It also explains how multiple processes can be run concurrently by switching between them when they enter waiting states, with the scheduler selecting the next ready process to run based on priorities. Job classes are divided into CPU-bound and I/O-bound processes, and spooling is used to share sequential peripherals by queuing output.
The document discusses assessing software complexity and security metrics from UML class diagrams for software reengineering. It proposes developing a Software Reverse Engineering Tool (SRET) that can automatically calculate metrics like coupling, cohesion, and security metrics from a UML class diagram generated from source code. This would help analysts and developers evaluate software metrics more quickly and efficiently during reengineering compared to manual methods. The tool would extract metrics based on rules applied to the class diagram to measure things like data access, operation access, and interactions between methods and attributes.
This document presents a power factor correction technique using average current-mode control for DC-DC boost converters. It uses a fuzzy logic controller to control the output voltage and PI controllers to correct the input current shape. The methodology section describes the circuit, including a rectifier, boost converter, and control blocks. It also discusses average current mode control, the simulation model built in MATLAB, and the design of the fuzzy logic controller with seven membership functions for both inputs and one output. The results section shows simulation waveforms demonstrating power factor correction with low input current harmonics and regulated output voltage. It concludes the fuzzy controller provides better dynamic response to load changes than PI control.
This document discusses using GIS software to identify the shortest and most economical route for a national highway alignment between Palani and Erode in Tamil Nadu, India. It considers factors like land use, geology, land value, and soil type by assigning weights and ranks to each theme. The themes are then overlaid in GIS to identify the most suitable highway alignment area. Conventional manual methods for route selection were difficult, time-consuming, and expensive compared to the proposed GIS-based approach.
This study analyzed the effectiveness of 5 domestic water filters in removing physical, chemical, and biological contaminants from various water sources. Testing was conducted over 10 months at 100%, 50%, and 0% of each filter's lifespan. Results showed the filters were good at removing organic impurities but failed to significantly reduce parameters like TDS, hardness, and chloride. Microbiological reduction was 95-99% effective. However, flow rates were very slow at 5-7 minutes per liter on average, decreasing further over the filters' lifespan. While the filters showed promise in improving water quality, the authors concluded their performance needs to be improved, particularly regarding flow rate and removal of inorganic parameters.
The document discusses the optimal bidding strategy in deregulated electricity markets. It proposes using a particle swarm optimization algorithm to determine the optimal bidding strategy for generators and large consumers. In a deregulated market, electricity generation, transmission, distribution, and retail sales are separated and opened to competition. This includes generating companies, large consumers who participate in demand bidding, and small consumers represented in aggregate form. The algorithm uses previous bidding data and a multi-round auction process to obtain the optimal bidding strategy, converging faster than Monte Carlo simulation.
This document discusses the construction of mixed sampling plans indexed through maximum allowable percent defective (MAPD) and acceptable quality level (AQL) using a conditional double sampling plan as the attribute plan and weighted Poisson distribution. Mixed sampling plans involve two stages - a variable plan followed by an attribute plan if needed. The paper presents a procedure to construct such mixed plans indexed by MAPD and AQL. Tables are constructed to allow easy selection of the sampling plan parameters. Weighted Poisson distribution is used as the baseline distribution to account for different importance levels of different outcomes.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
1) The document discusses data hiding in mazes using steganography techniques. It describes perfect mazes, imperfect mazes, and how mazes can be represented as graphs.
2) Existing maze-based data hiding methods are described, including representing the solution path as binary 1s and carving walls between embeddable cells and neighboring cells as 0s to hide bits.
3) The proposed method aims to increase data hiding capacity by embedding bits into multiple solution paths in the maze rather than just one path.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
This document summarizes a research paper that investigated the optimization of process parameters for electro-discharge machining (EDM) of AISI 4140 alloy steel. The researchers used a central composite design and response surface methodology to analyze the effects of pulse on time, gap voltage, flushing pressure, input current, and duty cycle on material removal rate and surface roughness. Mathematical models were developed relating the process parameters and responses. The results showed that material removal rate was most influenced by peak current and duty factor. The parameters were then optimized to maximize material removal rate while achieving the desired surface roughness.
This document summarizes research on minimizing stress in a parabolic leaf spring through simulated annealing optimization. It describes the structure and materials used for leaf springs. Finite element analysis was conducted on a CAD model of a parabolic leaf spring in CATIA. Simulated annealing was used to vary the camber and eye distance parameters to minimize von Mises stress. The optimization resulted in a camber of 90.395007 mm and eye distance of 1024.246478 mm, which reduced maximum stress.
The document proposes a framework called Semantic Conflicts Reconciliation (SCR) to detect and resolve data-level semantic conflicts when integrating heterogeneous data sources. SCR uses an ontology-based approach where data semantics are explicitly described during knowledge representation. At query time, an Interpretation Mediation Service can then automatically detect and resolve conflicts. Traditional approaches like global data standardization or pairwise data conversions between all sources are infeasible due to the large number of sources and conversions required. SCR aims to provide a more scalable solution through its ontology-based representation of semantics.
La Asamblea Nacional aprobó 25 leyes, 41 resoluciones y 15 convenios internacionales en 2010 para establecer los derechos del buen vivir y la reinstitucionalización del Estado. Entre las leyes más importantes se encuentran la Ley de Educación Superior, Ley de Servicio Público, reformas al Código Penal, y leyes para apoyar a migrantes y regular la planificación legislativa. La Asamblea también aprobó el presupuesto para 2011 con enfoque en inversión social y participó en foros internacionales para impulsar la inte
Nubilum: Resource Management System for Distributed CloudsGlauco Gonçalves
This thesis proposes a resource management system called Nubilum for distributed clouds (D-Clouds). D-Clouds provide resources across geographically distributed datacenters to address challenges of centralized cloud providers like latency and failure management. Nubilum considers the geographical locality of resources and provides a network as a service (NaaS) for connectivity. It offers solutions for discovery, monitoring, control and allocation of resources in D-Clouds to ensure quality of service while meeting developers' requirements. The thesis describes Nubilum and its allocation algorithms, and evaluates the algorithms' efficiency and effectiveness.
El documento discute la necesidad de expandir el acceso a la tecnología y las telecomunicaciones a toda la población ecuatoriana. Actualmente, el acceso a la tecnología es limitado, especialmente en las áreas rurales. El gobierno ecuatoriano está implementando proyectos como el Plan de Servicio Universal para mejorar la conectividad, pero se necesita un enfoque más coordinado y sostenible a largo plazo. También es importante promover un cambio de mentalidad para que la gente aproveche mejor las herramientas tecnoló
ATOS OFICIAIS SÃO GONÇALO 18 de julho de 2012jornalbocalivre
Este documento contém várias nomeações, exonerações e transferências de cargos em comissão na Prefeitura Municipal de São Gonçalo. Também aprova prestação de contas de três instituições que recebem recursos públicos para creches.
O documento descreve um projeto de inclusão digital em uma escola, com o objetivo de proporcionar aos alunos e à comunidade novas fontes de conhecimento através da tecnologia e preparar educadores para usar recursos digitais na educação e gestão escolar de forma colaborativa.
IRJET- Implementation of TPG-LFSR with Reseeding Pattern ValueIRJET Journal
This document discusses the implementation of a reseeding linear feedback shift register (RLFSR) for test pattern generation. RLFSR is used to generate pseudorandom test patterns for built-in self-test (BIST) to test circuits. It can reduce the number of test patterns needed and test time compared to traditional LFSR techniques. The proposed method uses a counter to generate seed values for the RLFSR to produce test patterns for the circuit under test. Experimental results demonstrate that the RLFSR approach can improve fault coverage while reducing storage and time requirements compared to other BIST methods.
IRJET- UART Testing under Built-In-Self-Test(BIST) using Verilog on FPGAIRJET Journal
This document discusses testing of a UART (Universal Asynchronous Receiver/Transmitter) chip using Built-In Self-Test (BIST) and implemented with Verilog on an FPGA. It proposes a BIST-enabled UART architecture that uses a linear feedback shift register (LFSR) as the test pattern generator and a multiple input shift register (MISR) as the response analyzer. The goal is to provide high test coverage with low hardware overhead. Key aspects of BIST and how it can test chips through embedded self-testing circuits like LFSRs and MISRs are described. The paper also discusses implementing and testing the proposed BIST-enabled UART design using Verilog on an FPGA to
The document discusses assessing software complexity and security metrics from UML class diagrams for software reengineering. It proposes developing a Software Reverse Engineering Tool (SRET) that can automatically calculate metrics like coupling, cohesion, and security metrics from a UML class diagram generated from source code. This would help analysts and developers evaluate software metrics more quickly and efficiently during reengineering compared to manual methods. The tool would extract metrics based on rules applied to the class diagram to measure things like data access, operation access, and interactions between methods and attributes.
This document presents a power factor correction technique using average current-mode control for DC-DC boost converters. It uses a fuzzy logic controller to control the output voltage and PI controllers to correct the input current shape. The methodology section describes the circuit, including a rectifier, boost converter, and control blocks. It also discusses average current mode control, the simulation model built in MATLAB, and the design of the fuzzy logic controller with seven membership functions for both inputs and one output. The results section shows simulation waveforms demonstrating power factor correction with low input current harmonics and regulated output voltage. It concludes the fuzzy controller provides better dynamic response to load changes than PI control.
This document discusses using GIS software to identify the shortest and most economical route for a national highway alignment between Palani and Erode in Tamil Nadu, India. It considers factors like land use, geology, land value, and soil type by assigning weights and ranks to each theme. The themes are then overlaid in GIS to identify the most suitable highway alignment area. Conventional manual methods for route selection were difficult, time-consuming, and expensive compared to the proposed GIS-based approach.
This study analyzed the effectiveness of 5 domestic water filters in removing physical, chemical, and biological contaminants from various water sources. Testing was conducted over 10 months at 100%, 50%, and 0% of each filter's lifespan. Results showed the filters were good at removing organic impurities but failed to significantly reduce parameters like TDS, hardness, and chloride. Microbiological reduction was 95-99% effective. However, flow rates were very slow at 5-7 minutes per liter on average, decreasing further over the filters' lifespan. While the filters showed promise in improving water quality, the authors concluded their performance needs to be improved, particularly regarding flow rate and removal of inorganic parameters.
The document discusses the optimal bidding strategy in deregulated electricity markets. It proposes using a particle swarm optimization algorithm to determine the optimal bidding strategy for generators and large consumers. In a deregulated market, electricity generation, transmission, distribution, and retail sales are separated and opened to competition. This includes generating companies, large consumers who participate in demand bidding, and small consumers represented in aggregate form. The algorithm uses previous bidding data and a multi-round auction process to obtain the optimal bidding strategy, converging faster than Monte Carlo simulation.
This document discusses the construction of mixed sampling plans indexed through maximum allowable percent defective (MAPD) and acceptable quality level (AQL) using a conditional double sampling plan as the attribute plan and weighted Poisson distribution. Mixed sampling plans involve two stages - a variable plan followed by an attribute plan if needed. The paper presents a procedure to construct such mixed plans indexed by MAPD and AQL. Tables are constructed to allow easy selection of the sampling plan parameters. Weighted Poisson distribution is used as the baseline distribution to account for different importance levels of different outcomes.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
1) The document discusses data hiding in mazes using steganography techniques. It describes perfect mazes, imperfect mazes, and how mazes can be represented as graphs.
2) Existing maze-based data hiding methods are described, including representing the solution path as binary 1s and carving walls between embeddable cells and neighboring cells as 0s to hide bits.
3) The proposed method aims to increase data hiding capacity by embedding bits into multiple solution paths in the maze rather than just one path.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
This document summarizes a research paper that investigated the optimization of process parameters for electro-discharge machining (EDM) of AISI 4140 alloy steel. The researchers used a central composite design and response surface methodology to analyze the effects of pulse on time, gap voltage, flushing pressure, input current, and duty cycle on material removal rate and surface roughness. Mathematical models were developed relating the process parameters and responses. The results showed that material removal rate was most influenced by peak current and duty factor. The parameters were then optimized to maximize material removal rate while achieving the desired surface roughness.
This document summarizes research on minimizing stress in a parabolic leaf spring through simulated annealing optimization. It describes the structure and materials used for leaf springs. Finite element analysis was conducted on a CAD model of a parabolic leaf spring in CATIA. Simulated annealing was used to vary the camber and eye distance parameters to minimize von Mises stress. The optimization resulted in a camber of 90.395007 mm and eye distance of 1024.246478 mm, which reduced maximum stress.
The document proposes a framework called Semantic Conflicts Reconciliation (SCR) to detect and resolve data-level semantic conflicts when integrating heterogeneous data sources. SCR uses an ontology-based approach where data semantics are explicitly described during knowledge representation. At query time, an Interpretation Mediation Service can then automatically detect and resolve conflicts. Traditional approaches like global data standardization or pairwise data conversions between all sources are infeasible due to the large number of sources and conversions required. SCR aims to provide a more scalable solution through its ontology-based representation of semantics.
La Asamblea Nacional aprobó 25 leyes, 41 resoluciones y 15 convenios internacionales en 2010 para establecer los derechos del buen vivir y la reinstitucionalización del Estado. Entre las leyes más importantes se encuentran la Ley de Educación Superior, Ley de Servicio Público, reformas al Código Penal, y leyes para apoyar a migrantes y regular la planificación legislativa. La Asamblea también aprobó el presupuesto para 2011 con enfoque en inversión social y participó en foros internacionales para impulsar la inte
Nubilum: Resource Management System for Distributed CloudsGlauco Gonçalves
This thesis proposes a resource management system called Nubilum for distributed clouds (D-Clouds). D-Clouds provide resources across geographically distributed datacenters to address challenges of centralized cloud providers like latency and failure management. Nubilum considers the geographical locality of resources and provides a network as a service (NaaS) for connectivity. It offers solutions for discovery, monitoring, control and allocation of resources in D-Clouds to ensure quality of service while meeting developers' requirements. The thesis describes Nubilum and its allocation algorithms, and evaluates the algorithms' efficiency and effectiveness.
El documento discute la necesidad de expandir el acceso a la tecnología y las telecomunicaciones a toda la población ecuatoriana. Actualmente, el acceso a la tecnología es limitado, especialmente en las áreas rurales. El gobierno ecuatoriano está implementando proyectos como el Plan de Servicio Universal para mejorar la conectividad, pero se necesita un enfoque más coordinado y sostenible a largo plazo. También es importante promover un cambio de mentalidad para que la gente aproveche mejor las herramientas tecnoló
ATOS OFICIAIS SÃO GONÇALO 18 de julho de 2012jornalbocalivre
Este documento contém várias nomeações, exonerações e transferências de cargos em comissão na Prefeitura Municipal de São Gonçalo. Também aprova prestação de contas de três instituições que recebem recursos públicos para creches.
O documento descreve um projeto de inclusão digital em uma escola, com o objetivo de proporcionar aos alunos e à comunidade novas fontes de conhecimento através da tecnologia e preparar educadores para usar recursos digitais na educação e gestão escolar de forma colaborativa.
IRJET- Implementation of TPG-LFSR with Reseeding Pattern ValueIRJET Journal
This document discusses the implementation of a reseeding linear feedback shift register (RLFSR) for test pattern generation. RLFSR is used to generate pseudorandom test patterns for built-in self-test (BIST) to test circuits. It can reduce the number of test patterns needed and test time compared to traditional LFSR techniques. The proposed method uses a counter to generate seed values for the RLFSR to produce test patterns for the circuit under test. Experimental results demonstrate that the RLFSR approach can improve fault coverage while reducing storage and time requirements compared to other BIST methods.
IRJET- UART Testing under Built-In-Self-Test(BIST) using Verilog on FPGAIRJET Journal
This document discusses testing of a UART (Universal Asynchronous Receiver/Transmitter) chip using Built-In Self-Test (BIST) and implemented with Verilog on an FPGA. It proposes a BIST-enabled UART architecture that uses a linear feedback shift register (LFSR) as the test pattern generator and a multiple input shift register (MISR) as the response analyzer. The goal is to provide high test coverage with low hardware overhead. Key aspects of BIST and how it can test chips through embedded self-testing circuits like LFSRs and MISRs are described. The paper also discusses implementing and testing the proposed BIST-enabled UART design using Verilog on an FPGA to
Fpga based efficient multiplier for image processing applications using recur...VLSICS Design
The Digital Image processing applications like medical imaging, satellite imaging, Biometric trait images
etc., rely on multipliers to improve the quality of image. However, existing multiplication techniques
introduce errors in the output with consumption of more time, hence error free high speed multipliers has
to be designed. In this paper we propose FPGA based Recursive Error Free Mitchell Log Multiplier
(REFMLM) for image Filters. The 2x2 error free Mitchell log multiplier is designed with zero error by
introducing error correction term is used in higher order Karastuba-Ofman Multiplier (KOM)
Architectures. The higher order KOM multipliers is decomposed into number of lower order multipliers
using radix 2 till basic multiplier block of order 2x2 which is designed by error free Mitchell log multiplier.
The 8x8 REFMLM is tested for Gaussian filter to remove noise in fingerprint image. The Multiplier is
synthesized using Spartan 3 FPGA family device XC3S1500-5fg320. It is observed that the performance
parameters such as area utilization, speed, error and PSNR are better in the case of proposed architecture
compared to existing architectures.
Enhanced Built-In Self Test for MSP 430IJTET Journal
The enhanced Built in self test (BIST) is a combined form of both hardware and software together to resolve the memory problem in self testing. So it automatically comprises own test using self test pattern generation. The implementation can be done using the microcontroller MSP 430 series. Here we are using the Xilinx software for compilation in the design implementation. Also its functional can be done using dynamic RAM and reduces the external testing methods also includes diagnosis of test.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
This document summarizes a research paper that proposes a modified March test algorithm for high-speed testing of SRAM using a built-in self-test (BIST) architecture. The BIST architecture includes a test controller, pattern generator, input multiplexer, and comparator. It aims to detect various RAM fault models including stuck-at faults, coupling faults, transition faults, and address decoder open faults. An improved version of the March test algorithm is implemented using microcoded BIST techniques for flexibility in applying test patterns.
Implementation of FSM-MBIST and Design of Hybrid MBIST for Memory cluster in ...Editor IJCATR
In current scenario, power efficient MPSoC’s are of great demand. The power efficient asynchronous MPSoC’s with
multiple memories are thought-off to replace clocked synchronous SoC, in which clock consumes more than 40% of the total power. It
is right time to develop the test compliant asynchronous MpSoC. In this paper, Traditional MBIST and FSM based MBIST schemes
are designed and applied to single port RAM. The results are discussed based on the synthesis reports obtained from RTL Complier
from Cadence. FSM based MBIST is power and area efficient method for single memory testing. It consumes 40% less power when
compared with traditional MBIST. But, in case of multiple memory scenarios, separate MBIST controllers are required to test each
individual memories. Thus this scheme consumes huge area and becomes inefficient. A novel technique for testing different memories
which are working at different frequencies is in need. Therefore, an area efficient Hybrid MBIST is proposed with single MBIST
controller to test multiple memories in an Asynchronous SoC. It also includes multiple test algorithms to detect various faults. An
Asynchronous SoC with DWT processor and multiple memories is discussed in this paper, which will used as Design under Test
[DUT] and Hybrid MBIST is built around it to test the heterogeneous memories. The design is coded in Verilog and Validated in
Spartan-3e FPGA kit.
Data Volume Compression Using BIST to get Low-Power Pseudorandom Test Pattern...IJMTST Journal
This project describes a low-power (LP) programmable generator capable of producing pseudorandom test patterns with desired toggling levels and enhanced fault coverage gradient compared with the best-to-date built-in self-test (BIST)- based pseudorandom test pattern generators. It is comprised of a linear finite state machine (a linear feedback shift register or a ring generator) driving an appropriate phase shifter, and it comes with a number of features allowing this device to produce binary sequences with preselected toggling (PRESTO) activity. We introduce a method to automatically select several controls of the generator offering easy and precise tuning. The same technique is subsequently employed to deterministically guide the generator toward test sequences with improved fault-coverage-to pattern-count ratios. Furthermore, this proposes an LP test compression method that allows shaping the test power envelope in a fully predictable, accurate, and flexible fashion by adapting the PRESTO based logic BIST (LBIST) infrastructure. The proposed architecture is extended in such that the patterns generated from PRPG is gone through CUT and then to TRA to perform ATE.
A Unique Test Bench for Various System-on-a-Chip IJECEIAES
This paper discusses a standard flow on how an automated test bench environment which is randomized with constraints can verify a SOC efficiently for its functionality and coverage. Today, in the time of multimillion gate ASICs, reusable intellectual property (IP), and system-ona-chip (SoC) designs, verification consumes about 70 % of the design effort. Automation means a machine completes a task autonomously, quicker and with predictable results. Automation requires standard processes with welldefined inputs and outputs. By using this efficient methodology it is possible to provide a general purpose automation solution for verification, given today’s technology. Tools automating various portions of the verification process are being introduced. Here, we have Communication based SOC The content of the paper discusses about the methodology used to verify such a SOC-based environment. Cadence Efficient Verification Methodology libraries are explored for the solution of this problem. We can take this as a state of art approach in verifying SOC environments. The goal of this paper is to emphasize the unique testbench for different SOC using Efficient Verification Constructs implemented in system verilog for SOC verification.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Reduced Test Pattern Generation of Multiple SIC Vectors with Input and Output...IJERA Editor
In recent years, the design for low power has become one of the greatest challenges in high-performance very
large scale integration (VLSI) design. Most of the methods focus on the power consumption during normal mode
operation, while test mode operation has not normally been a predominant concern. However, it has been found
that the power consumed during test mode operation is often much higher than during normal mode operation
[1]. This is because most of the consumed power results from the switching activity in the nodes of the circuit
under test (CUT), which is much higher during test mode than during normal mode operation [1]–[3]. In the
proposed pattern, each generated vector applied to each scan chain is an SIC vector, which can minimize the
input transition and reduce test power. In VLSI testing, power reduction is achieved by increasing the correlation
between consecutive test patterns.
International Journal of Engineering Research and DevelopmentIJERD Editor
Electrical, Electronics and Computer Engineering,
Information Engineering and Technology,
Mechanical, Industrial and Manufacturing Engineering,
Automation and Mechatronics Engineering,
Material and Chemical Engineering,
Civil and Architecture Engineering,
Biotechnology and Bio Engineering,
Environmental Engineering,
Petroleum and Mining Engineering,
Marine and Agriculture engineering,
Aerospace Engineering.
Vlsi Design of Low Transition Low Power Test Pattern Generator Using Fault Co...iosrjce
Now a day’s highly integrated multi layer board with IC’s is virtually impossible to be accessed
physically for testing. The major problem detected during testing a circuit includes test generation and gate to
I/O pin problems. In design of any circuit, consuming low power and less hardware utilization is an important
design parameter. Therefore reliable testing methods are introduced which reduces the cost of the hardware
required and also power consumed by the device. In this project a new fault coverage test pattern generator is
generated using a linear feedback shift register called FC-LFSR which can perform fault analysis and reduces
the total power of the circuit. In this test, it generates three intermediate patterns between the random patterns
which reduces the transitional activities of primary inputs so that the switching activities inside the circuit under
test will be reduced. The test patterns generated are applied to c17 benchmark circuit, whose results with fault
coverage of the circuit being tested. The simulation for this design is performed using Xilinx ISE software using
Verilog hardware description language
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Paper Link: https://eprint.iacr.org/2024/257
zkStudyClub - LatticeFold: A Lattice-based Folding Scheme and its Application...
Dt25720726
1. C.Ravishankar reddy Lecturer, Dr. V. Sumalatha Associate professor, P.Venkata Gopikumar
PG Scholar / International Journal of Engineering Research and Applications (IJERA) ISSN:
2248-9622 www.ijera.com Vol. 2, Issue 5, September- October 2012, pp.720-726
Fault Detection By Using Random And Deterministic Test
Pattern Techniques In A Mixed-Mode BIST Environment
C.Ravishankar reddy Lecturer, Dr. V. Sumalatha Associate professor, &
P.Venkata Gopikumar PG Scholar
Department of Electronics & Communication Engineering
Jawaharlal Nehru Technological University
Anantapur, India
Abstract
A method for testing embedded core pseudorandom pattern generation (PRPG) are called
based system chips is to use a built-in-self-test random-pattern-resistant (RPR) faults. To increase
(BIST). A mixed-mode (Partial pattern matching the probability of detecting the RPR faults by
and multi-control-sequence) built-in-self-test following the three categories. But these three
(BIST) that brings two new techniques. They are categories have drawbacks
partial pattern matching and multi control The modification of circuit under test
sequence. Partial pattern matching allows the The use of weighted random pattern
reduction of the number of patterns used for generation.
detecting random-pattern-resistant faults without The mixed mode approach.
using the fault simulation. A multi control
sequence is used to guide the linear feedback shift The first category improves fault coverage
register (LFSR) to generate these patterns at by redesigning or inserting test points. It is not
application time. The main advantages of this always possible because of performance restriction
method are reduction of the test data volume, or intellectual property (IP) reasons. The second
require less time to test the application and its category is also to increase the probability for test
reusability for logic cores on a system-on-chip patterns to detect RPR faults, but it is not efficient
(SOC). the third category consists of two phases: In the first
phase, PR patterns are applied to detect the faults
Index Terms—-Built in self-test (BIST), Linear here fault coverage is done by 60% to 80% only. In
feedback shift register (LFSR), random-pattern- the second phase, deterministic test patterns are
resistant (RPR) faults, system-on-chips (SOCs). injected to find the remaining faults. The
deterministic patterns are generated by the LFSR[1]
1. Introduction by reseeding are Appling a control signal that
Design integration can be increased by matches the output of the LFSR to the desired
making the ICs small size and power should be low. deterministic patterns.
The requirements for small size and low-power ICs A new technique for the generation of the
have caused a significant increase in design test patterns for RPR faults by controlling the LFSR
integration. the integration several designs (cores) at the time of test application. This technique is
into a single monolithic IC which results in a system- called partial pattern matching. Select a BIST[2]
on-chip (SOC). The number of cores integrated in a using a controllable LFSR with multiple scan chains
SOC is rapidly increasing, resulting in large amount to generate deterministic patterns. In this approach,
of test data. To achieve the good test quality for the the system integrator is able to develop the core’s
complex SOC by using the finite number of I/Os is a tests without knowing the actual implementation of
very difficult task. The amount of time required for the core because providing deterministic test patterns
this type of test application is high, it is also a big and the S-matrix by the core provider. Hence, the
problem to overcome all these drawbacks and for method promotes design and test reuse without
testing embedded core based system chips is to use a changing or revealing IP information.
built-in self-test (BIST). The advantages of built-in Partial-matching technique along with
cell-test (BIST) are simplicity, flexibility and low multiple scan chains the BIST greater using a
overhead. The test pattern generator for the BIST is controllable LFSR, the goals such are
pseudorandom (PR) test pattern generator for its on- To reduce the test data volume
chip test pattern generation. To shorten the test application time
Pseudorandom test pattern generation Reusability for logic cores
(PRPG) can be implemented by using a linear These three major goals can be achieved by
feedback shift register. LFSR has several advantages. mixed mode BIST. When comparing this method
They are low overhead, scalability and reuse mixed-mode BIST environment to other mixed-mode
capability. Faults that are difficult to detect by approaches. In
720 | P a g e
2. C.Ravishankar reddy Lecturer, Dr. V. Sumalatha Associate professor, P.Venkata Gopikumar
PG Scholar / International Journal of Engineering Research and Applications (IJERA) ISSN:
2248-9622 www.ijera.com Vol. 2, Issue 5, September- October 2012, pp.720-726
Most mixed modes, the test flow is outlined in Fig.
1(a).
Our methodology is shown in Fig. 1(b):
First, a deterministic ATPG is used. The patterns are
then partially matched. The remaining patterns are C
generated by applying a control sequence to the
LFSR[1]. In our architecture shown in Fig. 2: It U
consists of controllable LFSR and phase shifter and T
scan chains and it is connected to the multi input
signature register(MISR) from this it is connected to
To
embedded memory from this it is connected to
LFSR
BIST[2] controller.
Design Design
Fault Simulation with ATPG T1
PRPG
Deterministic
RPR Faults patterns
PRPG
ATPG
Partial Matching
Phase shifter
Deterministic
Controllable
patterns Remaining
PRPG patterns
Tm-1
MISR
Second Phase of Mixed- Control sequences
Mode
(a) (b)
Improved test Improved test
Quality Quality
(a) (b)
Fig. 1. Mixed-mode flow Combinational
In many of the mixed modes, first the test logic
flow is done by using a PR pattern, fault simulation
is performed, and the RPR faults are identified. Then,
a deterministic automatic test pattern generation
(ATPG) is used to generate patterns for RPR faults.
Embedded
BIST Memory
Controller
Fig. 2. Proposed testing architecture.
The second phase of the mixed-mode approach
is then applied that is deterministic patterns are
applied to target remaining faults. In our
methodology first, a deterministic ATPG is used. The
patterns are then partially matched. The remaining
patterns are generated by applying control sequence
to the LFSR. In our proposed method there are many
advantages. First, fault simulation is eliminated but it
is not in the case of other mixed modes. Second, the
721 | P a g e
3. C.Ravishankar reddy Lecturer, Dr. V. Sumalatha Associate professor, P.Venkata Gopikumar
PG Scholar / International Journal of Engineering Research and Applications (IJERA) ISSN:
2248-9622 www.ijera.com Vol. 2, Issue 5, September- October 2012, pp.720-726
partial pattern matching increases the number of hits Fig. 3 (b) S-graph of a design.
and hence leaves a fewer number of RPR patterns to
require LFSR control signals. The shorter the control a
sequence, the smaller the storage needed on the chip.
1 a
In section II, we describe the partial matching 1
A
scheme. In section III, we describe the multiple- 7
control sequence(MCS). Simulation results are g a
presented in section IV, synthesis results are o a
presented in section V, and in section VI, we present 1 C
our results. 0
a
2. PARTIAL MATCHING a
To maximize the fault coverage, all g 2
5
specified bits of the deterministic test patterns have 1
to be fully matched by the PR patterns being a
produced by the LFSR. If there are many specified
bits in the test pattern of a long scan chain, but it is 3
difficult for PR pattern to hit any deterministic a
g a
patterns with a full pattern match. This will result in 4
huge number of test patterns that are not covered, 2 a B
1
this drawback can be eliminated in our new partial 0
6
matching technique which analyzes the binary S-
matrix. This binary S-matrix and utilizes the a
topology of the logic cones. This approach increases
9
the possibility of patterns matching and hence
reduces the size of the required control sequence. g
Circuit Modeling
3
The binary S-matrix can be constructed
from the S-graph [6] that is G = (V, E), where V is
the set of vertices representing the scan cells in the a
circuit, E is the set of edges representing connectivity Fig. 3. (a) ISCAS benchmark circuit S27.
8
between the scan cells. The first step of the test
preparation is to generate the binary S-matrix [6] for Using Logic Cones to Partition
the cores. An entry S (i, j) =1 indicates that scan cell A single deterministic test pattern generated
i is feeding into scan cell j. And S (I, j) =0 indicates by an ATPG usually detects more than one fault in
that scan cell i is not feeding into scan the desire. When the pattern is captured by the flip-
cell j. Using the S-matrix confirms our approach with flops, the new input of any flip flop represents the
respect to testing without revealing IP information response of pattern for faults within the
because the S-matrix is represented by the combinational circuit cone converging at this flip
connectivity of scan cells without giving structure of flop. Logic cones are nothing but logic gates or
the logic circuits. simply combinational circuits each sub pattern
In the similar way the scan chains can also be corresponds to a logic cone of the design, which may
constricted, in such way that the scan cells in the contain multiple faults of the logic gates. For
same scan chain are independent of each other. The example deterministic test pattern expanded into
aim was to make the set of linear equations, which three sub patterns each sub pattern detects faults in
are necessary for the reseeding of an LFSR. In other the corresponding logic cone sub patterns have more
words all the inputs of any logic cone are always in ”don’t care” bits than the original pattern. Hence,
one scan chain but in our approach where the inputs they are easier to match with the PR patterns then the
of a logic cone can be in any scan chain. original deterministic test pattern. Now a partial
A B C pattern matching technique is to be applied to the sub
patterns as an enhancement to the full pattern
A 1 0 0
matching technique, which has been applied to the
A 1 1 0
original deterministic test patterns.
B
The partial matching technique consists of the
C following three steps.
C 1 0 1
Form sub patterns for each deterministic
B
(c). Binary S-matrix of a pattern using a cone-masking approach.
design Generate the PR test patterns by simulating
the LFSR and match them to sub patterns.
722 | P a g e
4. C.Ravishankar reddy Lecturer, Dr. V. Sumalatha Associate professor, P.Venkata Gopikumar
PG Scholar / International Journal of Engineering Research and Applications (IJERA) ISSN:
2248-9622 www.ijera.com Vol. 2, Issue 5, September- October 2012, pp.720-726
Combine the remaining unmatched sub pattern counter counts the number of capture cycles
patterns that are related to the each original that occur during each test execution phase.
deterministic test pattern and update the
final set of deterministic test patterns.
U0
M
M0
X15
T0
S0
U1
Phase shifter
z M1
X14 T1
S1
X13
Um-1 X12
Mm-1
Tm-1
Sm-1
X0
Fig. 4. Controlling the LFSR
TABLE I
The original deterministic test patterns are
split in to sub patterns for each deterministic test Sub patterns for deterministic pattern
pattern the number of sub patterns is equal to the
number of columns of the S-matrix that have at least Deterministic Sub-Patterns Logic
one entry of a “1” . The value of bit i of sub pattern j Pattern
cone
A B C
is the same as the value of bit i of the deterministic A B C
test pattern if and only if S [i, j] is 1 otherwise it is
unspecified bit(x). 0 1 1 0 x x 1
In this method, there existing a phase x 1 x 2
shifter [4] and multiple scan chains. There are two
test execution phases. During the first test phase, the x x 1 3
LFSR is freely ran for a user specified number of N
cycles to generate PR test patterns for easily The circuit shown in Fig. 3(a) is the ISCAS
detectable faults. The number of PR test patterns is (International standard circuit and system)
the same as the used in all cores but with less test benchmark circuit S27. It can be represented by the
application time because of multiple scan chains. In S-graph shown in Fig. 3(b). The corresponding
the second test phase MCSs are used to direct the binary S-matrix is shown in Fig. 3(c). As per our
LFSR to generate the remaining patterns to detect the methodology first Deterministic ATPG is used and it
RPR faults. is found that as 011.This deterministic pattern is then
Along with the phase shifter [4] and multiple scan split into three sub-patterns. Each sub pattern
chains there existing also a BIST controller. A corresponds to a logic cone of the design. Number of
pattern counter and a bit counter are part of the BIST logic for the circuit in Fig. 3(a), Table I shown
controller. The bit counter keeps track of the number deterministic test pattern (column 1) expanded into
of test data bits being shifted into scan chains. The three sub patterns. In the circuit fault was injected at
723 | P a g e
5. C.Ravishankar reddy Lecturer, Dr. V. Sumalatha Associate professor, P.Venkata Gopikumar
PG Scholar / International Journal of Engineering Research and Applications (IJERA) ISSN:
2248-9622 www.ijera.com Vol. 2, Issue 5, September- October 2012, pp.720-726
the a3 this fault is not identified by the random the body field Si, and Si is equal to one the advantage
pattern and it is detected by deterministic pattern at of MCS is to control any number of scan chain.
the 011.once after finding the deterministic pattern
and again the faults are injected at the a3, a4 and 4. Simulation results
these faults are determined by random pattern and
those faults which are not covered by random pattern
are identified by deterministic pattern test generation.
Thus all the faults will be determined by this method,
by applying both random pattern test generation and
deterministic pattern test generation, when s=0 the
controllable LFSR [3] generate random test patterns
and when s=1 it will generate the deterministic test
patterns.
3. MULTICONTROL SEQUENCES
BIST controller allows the LFSR to freely
run for a user defined number of capture cycles N it
begins to control the LFSR.The method of
deterministic bits presented a PRPG register to feed
the LFSR seeds for generating the desired patterns in
a multiple scan chain design For controlling the
LFSR, using an MCS to direct it and to generate and
apply the desired deterministic patterns in a multiple
scan design. The MCS consists of two vectors U=
(U0, U1, U2…..Um-1) and S= (S0, S1, S2……Sm-1). The
U vector was directly injected through multiplexers
to scan chains. All multiplexers have been moved to
the front of LFSR to improve both the test time and
test data volume.
Phase shifters structure is based on the STUMPS
architecture, one of the scan chains [5] is directly fed Fig. 5. Random pattern test generation.
from the left most tap of the LFSR while other chains
are fed from the phase shifter all the patterns
supplied to each scan chains can be controlled. For
example assume that four scan chain being controlled
by four taps from the phase shifter deterministic test
patterns indicated on These scan chains are (T0, T1,
T2, T3) respectively. There are more advantages in
using multi control to guide the LFSR to feed the
target test data to the scan chains. In most of the
cases only a few control sequences in some scan
chains have to be specified while the remaining
contents in the scan change are automatically
matched to deterministic patterns. Therefore the rest
of control sequences do not need to be specified.
This further reduces the test data storage
requirement.
The data format for the MCS consists of two
and fields: a header and a body. The header specifies
the logic values for the multiplexer selectors, body
holds the MCSs U0, U1………Um-1. If the
deterministic pattern for the ith scans chain consists
of only unspecified bits then the corresponding ith
control sequence Ui is not needed to create the
desires values of deterministic patterns. Therefore, Si
is equal to zero, Ui can be skipped from the body
field. However even If there is only one specified bit
to be controlled in a deterministic pattern the Fig. 6. Deterministic test pattern generation.
corresponding control sequence Ui must be include in
724 | P a g e
6. C.Ravishankar reddy Lecturer, Dr. V. Sumalatha Associate professor, P.Venkata Gopikumar
PG Scholar / International Journal of Engineering Research and Applications (IJERA) ISSN:
2248-9622 www.ijera.com Vol. 2, Issue 5, September- October 2012, pp.720-726
Fig.10.S-matrix and deterministic test pattern
generation.
Fig. 7. S-graph and S-matrix.
Fig. 8. ISCAS benchmark circuit S27.
Fig. 11. ISCAS benchmark circuit S27.
5. Synthesis result
6. Conclusion
In conclusion, a new approach that is
mixed-mode BIST that makes use of a partial-
matching technique to facilitate the generation of
patterns for RPR faults. The test application mode
uses a controllable LFSR for a multiple-scan-chain
configuration. We have analyzed the design through
the creation of a binary S-matrix and the
identification of logic cones. Then, we have applied
the partial pattern matching to filter the RPR faults.
In addition, we have generated an MCS to guide the
LFSR to generate the desired patterns instead of
applying the whole deterministic test. the fault
coverage as high as intended by the deterministic
test, we have succeeded in reducing both the test data
volume and the test application time. Moreover, in
comparison with [22], both the test sequence length
and the hardware overhead are much lower.
Fig. 9. Random pattern test generation
7. Acknowledgment
P.Venkata GopiKumar would like to thank
C .Ravishankar Reddy, who had been guiding
through out to complete the work successfully, and
725 | P a g e
7. C.Ravishankar reddy Lecturer, Dr. V. Sumalatha Associate professor, P.Venkata Gopikumar
PG Scholar / International Journal of Engineering Research and Applications (IJERA) ISSN:
2248-9622 www.ijera.com Vol. 2, Issue 5, September- October 2012, pp.720-726
would also like to thank the HOD, ECE Department
and other Professors for extending their help &
support in giving technical ideas about the paper and
motivating to complete the work effectively &
successfully
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