The document describes a novel FPGA implementation of an image scaling processor using bilinear interpolation. The proposed method uses sharpening and clamp filters as pre-filters to the bilinear interpolator in order to improve image quality during scaling. The bilinear interpolation algorithm was chosen due to its lower complexity compared to other methods. The design was implemented in Verilog and synthesized for an FPGA, achieving a maximum frequency of 215.64MHz for 64x64 grayscale images. The hardware resources required were moderately lower than other algorithms.