Applications using D Flip-flop Serial to Parallel Data Converter Parallel to Serial Data Converter JK Flip-flop Why is JK flip-flop named so? Preset and Clear Applications using JK Flip-flops Frequency Dividers

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Session 22: Focus
 Applications using D Flip-flop
◦ Serial to Parallel Data Converter
◦ Parallel to Serial Data Converter
 JK Flip-flop
◦ Why is JK flip-flop named so?
◦ Preset and Clear
 Applications using JK Flip-flops
◦ Frequency Dividers

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Applications using D-Flip-flops

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Example 3: Serial to Parallel Data Converter
 Serial to parallel data converter
 The serial data is shifted in at the positive edge of every clock
pulse
 After four clock pulses the parallel data is available at Q3Q2Q1Q0
> CLK> CLK> CLK> CLK
Positive Edge Triggered
D flip-flops
Added an
Inverter
To CLR

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Example 4: Parallel to Serial Data Converter
 Parallel to serial data converter
 On the first CLK pulse D0 to D3 get latched to the flip-flops (FF)
◦ With WRITE/SHIFT being LOW (latching parallel data)
 On subsequent CLK pulses, the latched data moves left to right
◦ With WRITE/SHIFT being HIGH (shifting the latched data out)
 D3 keeps moving in. At the end of 4 CLKs, all FFs will have D3
D3 D2 D1 D0
D3 D2 D1 D0D3 D2 D1 D0

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Why is JK-Flip-flop
named so?

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Why is JK Flip-flop named so?
 The choice of the letters "JK" in the JK flip flop do have
significance.
 The JK flip flop was named after Jack Kilby, the Texas
Instruments (TI) engineer that invented the integrated
circuit (IC) in 1958. Won Noble prize in physics in 2000.
 The modified RS circuit that eliminated race conditions
was named JK in his honor.
7
The first
IC built by
JK in 1958

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JK-Flip-flop
Preset and Clear

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JK Flip-flop (Preset and Clear)
 Preset (PRE) and Clear (CLR) are
two asynchronous inputs to the JK
flip-flops
 It is independent of clock signal
 These signals can be applied to the flip-
flop at any point in time
 Preset signal forces the Q to be 1
where as Clear (CLR) signal makes Q
as zero
 They override the synchronous
inputs, J, K and Clk
 Both PRE and CLR are active low
signals

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Quiz 1: Draw the output (Q) waveform

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Applications using JK-Flip-flops

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Quiz 2: What is the output (Q)?
Frequency
Division
By 2
Q output
is CLK/2

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Session 22: Summary
 Applications using D Flip-flop
◦ Serial to Parallel Data Converter
◦ Parallel to Serial Data Converter
 JK Flip-flop
◦ Why is JK flip-flop named so?
◦ Preset and Clear
 Applications using JK Flip-flops
◦ Frequency Dividers

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References
Ref 1 Ref 2