Digital Design Session 19

Digital Design – © 2020 Mouli Sankaran Email: mouli.sankaran@yahoo.com 2
Session 19: Focus
 Edge-triggered D Flip-flops
◦ Positive edge-triggered D Flip-flop Implementation
◦ Logic Symbol
 JK Flip-flop
◦ Implementation

Positive Edge-triggered
D Flip-flop

Positive Edge-triggered D Flip-flop
D = 1
The state before
0-to-1
Transition is
Captured
0
Assume D = 1
1
The value (1) of D prior to
the clk transition 0 to 1 is
captured as Q
S
R
S’ R’
When the clk is 0
Q is disconnected from D
Since S’R’ are 11 After latching on 0-to-1 clk transition, Q is disconnected from D

D = 0
The state before
0-to-1
Transition is
Captured
0
1
Assume D = 0
1
The value (0) of D while
The clk was zero is
Captured as Q
S
R
When the clk is 0

A Positive Edge-triggered D Flip-flop
 The value that is produced at the output (Q) of the flip-flop is
the value that was stored in the master stage immediately
before the positive edge occurred
 The logic symbol of the positive edge-triggered D-flip-flop is
give above
QThe state before
0-to-1
Transition is
Captured
> is the dynamic indicator

Level and Edge Triggering of Flip-flops

D = 1: with animation
The state before
0-to-1
Transition is
Captured
0
0
0
1
1
1
1
1
0
0
0
Assume D = 1
1
1
1
1
0
0
1
The value (1) of D prior to
the clk transition 0 to 1 is
captured as Q
S
R
1
1
1
0
0
S’ R’
When the clk is 0

D = 0: with animation
The state before
0-to-1
Transition is
Captured
0
0
0
1
1
0
1
1
1
1
1
Assume D = 0
1 1
1
0
1
1
0
The value (0) of D while
The clk was zero is
Captured as Q
S
R
0
1
1
When the clk is 0

JK Flip-flop

Other Flip-flops with D Flip-flop
 D Flip-flop is the simplest flip-flop that can be built with a less
number of logic gates
 In a typical Integrated Chip has millions of logic gates and
flips-flops inside them
 Other types of flip-flops are built using the D flip-flop
 J-K Flip-Flop
 T Flip-flop

When Q is 0 initially
JK Flip-flop – (JK = 00)
0
1
0
1
0
0
0
0
0
1
1
0
1
0
0
0
0
1
1
1

JK Flip-flop (JK = 01) - Reset
0
1
0
1
1
0
0
0
0
0
1
0
1
0
1
0
0
0
0
0
0
New
value

JK Flip-flop (JK = 10) - Set
0
1
0
1
0
1
1
0
1
1
1
0
1
0
0
1
0
1
1
1
1
New
value

JK Flip-flop (JK = 11) - Complement
0
1
0
1
1
1
1
0
1
0
1
0
1
0
1
1
0
0
0
0
1
New
value
0
New
value

Quiz 1: Draw the output (Q) waveform
Assume that the flip-flop
is initially RESET
This is Negative edge-triggered

Quiz 2: Draw the output (Q) waveform
Assume that the flip-flop
is initially RESET
This is Positive edge-triggered

Session 19: Summary
 Latches and Flip-flops
◦ Level and Edge-triggered clocks
 Edge-triggered D Flip-flops
◦ Negative edge-triggered
◦ Positive edge-triggered
 JK Flip-flop
◦ Implementation

References
Ref 1 Ref 2

Digital Design Session 19

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Digital Design Session 19