In this Technical era the high speed and low area of VLSI chip are very- very essential factors. Day by day number of transistors and other active and passive elements are growing on VLSI chip. In Integral part of the processor adders play an important role. In this paper we are using proposed kogge-stone adders for binary addition to reduce the size and increase the efficiency or processors speed. Proposing kogge stone adder provides less components, less path delay and better speed compare to other existing kogge stone adder and other adders. Here we are comparing the kogge stone adders of different-different word size from other adders. The design and experiment can be done by the aid of Xilinx 14.1i Spartan 3 device family.
Efficient Design of Ripple Carry Adder and Carry Skip Adder with Low Quantum ...IJERA Editor
The addition of two binary numbers is the important and most frequently used arithmetic process on
microprocessors, digital signal processors (DSP), and data-processing application-specific integrated circuits
(ASIC). Therefore, binary adders are critical structure blocks in very large-scale integrated (VLSI) circuits.
Their effective application is not trivial because a costly carry spread operation involving all operand bits has to
be achieved. Many different circuit constructions for binary addition have been planned over the last decades,
covering a wide range of presentation characteristics. In today era, reversibility has become essential part of
digital world to make digital circuits more efficient. In this paper, we have proposed a new method to reduce
quantum cost for ripple carry adder and carry skip adder. The results are simulated in Xilinx by using VHDL
language.
In this project 31 % area delay product reduction is possible with the use of the CSLA based 32 bit unsigned parallel multiplier than CLAA based 32 bit unsigned parallel multiplier
Verilog Implementation of an Efficient Multiplier Using Vedic MathematicsIJERA Editor
In this paper, the design of a 16x16 Vedic multiplier has been proposed using the 16 bit Modified Carry Select Adder and 16 bit Kogge Stone Adder. The Modified Carry Select Adder incorporates the Binary to Excess -1 Converter (BEC) and is known to be the fastest adder as compared to all the conventional adders. The design is implemented using the Verilog Hardware Description Language and tested using the Modelsim simulator. The code is synthesized using the Virtex-7 family with the XC7VX330T device. The Vedic multiplier has applications in Digital Signal Processing, Microprocessors, FIR filters and communication systems. This paper presents a comparison of the results of 16x16 Vedic multiplier using Modified Carry Select Adder and 16x16 Vedic Multiplier using Kogge Stone Adder. The results show that 16x16 Vedic Multiplier using Modified Carry Select Adder is more efficient and has less time delay as compared to the 16x16 Vedic Multiplier using Kogge Stone Adder.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Implementation and Comparison of Efficient 16-Bit SQRT CSLA Using Parity Pres...IJERA Editor
In Very Large Scale Integration (VLSI) outlines, Carry Select Adder (CSLA) is one of the quickest adder utilized as a part of numerous data processing processors to perform quick number crunching capacities. In this paper we proposed the design of SQRT CSLA using parity preserving reversible gate (P2RG). Reversible logic is emerging field in today VLSI design. In conventional circuits, the logic gates such as AND gate, OR gate is irreversible in nature and computing with irreversible logic results in energy dissipation. This problem can be circumvented by using reversible logic. In ideal condition, the reversible logic gate produces zero power dissipation. The proposed design is efficient in terms of delay as compare to irreversible SQRT CSLA. The simulation is done using Xilinx.
Power and Delay Analysis of Logic Circuits Using Reversible GatesRSIS International
This paper determines the propagation delay and on
chip power consumed by each basic and universal gates and
basic arithmetic functions designed using existing reversible
gates through VHDL. Hence a designer can choose the best
reversible gates to use for any logic circuit design. The paper
does a look up table analysis of truth tables of the reversible
gates to find the occurrence of the AND OR, NAND, NOR and
basic arithmetic functions, useful to build complex combinational
digital logic circuits.
Implementation of Efficiency CORDIC Algorithmfor Sine & Cosine GenerationIOSR Journals
Abstract: This paper presents an area-time efficient coordinate rotation digital computer (CORDIC) algorithm that completely eliminates the scale-factor. A generalized micro-rotation selection technique based on high speed most-significant-1-detection obviates the complex search algorithms for identifying the micro-rotations. This algorithm is redefined as the elementary angles for reducing the number of CORDIC iterations. Compared to the existing re-cursive architectures the proposed one has 17% lower slice-delay product on Xilinx Spartan XC2S200E device. The CORDIC processor pro-vides the flexibility to manipulate the number of iterations depending on the accuracy, area and latency requirements. Index Terms—coordinate rotation digital computer (CORDIC), cosine/sine, field-programmable gate array(FPGA),most-significant-1, recursive architecture.
Efficient Design of Ripple Carry Adder and Carry Skip Adder with Low Quantum ...IJERA Editor
The addition of two binary numbers is the important and most frequently used arithmetic process on
microprocessors, digital signal processors (DSP), and data-processing application-specific integrated circuits
(ASIC). Therefore, binary adders are critical structure blocks in very large-scale integrated (VLSI) circuits.
Their effective application is not trivial because a costly carry spread operation involving all operand bits has to
be achieved. Many different circuit constructions for binary addition have been planned over the last decades,
covering a wide range of presentation characteristics. In today era, reversibility has become essential part of
digital world to make digital circuits more efficient. In this paper, we have proposed a new method to reduce
quantum cost for ripple carry adder and carry skip adder. The results are simulated in Xilinx by using VHDL
language.
In this project 31 % area delay product reduction is possible with the use of the CSLA based 32 bit unsigned parallel multiplier than CLAA based 32 bit unsigned parallel multiplier
Verilog Implementation of an Efficient Multiplier Using Vedic MathematicsIJERA Editor
In this paper, the design of a 16x16 Vedic multiplier has been proposed using the 16 bit Modified Carry Select Adder and 16 bit Kogge Stone Adder. The Modified Carry Select Adder incorporates the Binary to Excess -1 Converter (BEC) and is known to be the fastest adder as compared to all the conventional adders. The design is implemented using the Verilog Hardware Description Language and tested using the Modelsim simulator. The code is synthesized using the Virtex-7 family with the XC7VX330T device. The Vedic multiplier has applications in Digital Signal Processing, Microprocessors, FIR filters and communication systems. This paper presents a comparison of the results of 16x16 Vedic multiplier using Modified Carry Select Adder and 16x16 Vedic Multiplier using Kogge Stone Adder. The results show that 16x16 Vedic Multiplier using Modified Carry Select Adder is more efficient and has less time delay as compared to the 16x16 Vedic Multiplier using Kogge Stone Adder.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Implementation and Comparison of Efficient 16-Bit SQRT CSLA Using Parity Pres...IJERA Editor
In Very Large Scale Integration (VLSI) outlines, Carry Select Adder (CSLA) is one of the quickest adder utilized as a part of numerous data processing processors to perform quick number crunching capacities. In this paper we proposed the design of SQRT CSLA using parity preserving reversible gate (P2RG). Reversible logic is emerging field in today VLSI design. In conventional circuits, the logic gates such as AND gate, OR gate is irreversible in nature and computing with irreversible logic results in energy dissipation. This problem can be circumvented by using reversible logic. In ideal condition, the reversible logic gate produces zero power dissipation. The proposed design is efficient in terms of delay as compare to irreversible SQRT CSLA. The simulation is done using Xilinx.
Power and Delay Analysis of Logic Circuits Using Reversible GatesRSIS International
This paper determines the propagation delay and on
chip power consumed by each basic and universal gates and
basic arithmetic functions designed using existing reversible
gates through VHDL. Hence a designer can choose the best
reversible gates to use for any logic circuit design. The paper
does a look up table analysis of truth tables of the reversible
gates to find the occurrence of the AND OR, NAND, NOR and
basic arithmetic functions, useful to build complex combinational
digital logic circuits.
Implementation of Efficiency CORDIC Algorithmfor Sine & Cosine GenerationIOSR Journals
Abstract: This paper presents an area-time efficient coordinate rotation digital computer (CORDIC) algorithm that completely eliminates the scale-factor. A generalized micro-rotation selection technique based on high speed most-significant-1-detection obviates the complex search algorithms for identifying the micro-rotations. This algorithm is redefined as the elementary angles for reducing the number of CORDIC iterations. Compared to the existing re-cursive architectures the proposed one has 17% lower slice-delay product on Xilinx Spartan XC2S200E device. The CORDIC processor pro-vides the flexibility to manipulate the number of iterations depending on the accuracy, area and latency requirements. Index Terms—coordinate rotation digital computer (CORDIC), cosine/sine, field-programmable gate array(FPGA),most-significant-1, recursive architecture.
International Journal of Computational Engineering Research(IJCER) is an intentional online Journal in English monthly publishing journal. This Journal publish original research work that contributes significantly to further the scientific knowledge in engineering and Technology.
Duet advancement of new technology in the field of VLSI and Embedded system, there is an increasing demand of high speed and low power consumption processor. Speed of processor greatly depends on its multiplier as well as adder performance. Due to which high speed adder architecture become important. Sever a ladder architecture designs have been developed to increase the efficiency of the adder. In this paper, we introduce an architecture that performs high speed modified carry select adder using boot hen coder (BEC) Technique. Booth encoder, Mathematics is an ancient Indian system of Mathematics. Here we are introduced two carry select based design. These designs are implementation Xilinx Vertex device family.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
A CORDIC based QR Decomposition Technique for MIMO Detection IJECEIAES
CORDIC based improved real and complex QR Decomposition (QRD) for channel pre-processing operations in (Multiple-Input Multiple-Output) MIMO detectors are presented in this paper. The proposed design utilizes pipelining and parallel processing techniques and reduces the latency and hardware complexity of the module respectively. Computational complexity analysis report shows the superiority of our module by 16% compared to literature. The implementation results reveal that the proposed QRD takes shorter lat ency compared to literature. The power consumption of 2x2 real channel matrix and 2x2 complex channel matrix was found to be 12mW and 44mW respectively on the state-of-the-art Xilinx Virtex 5 FPGA.
Cost Efficient Design of Reversible Adder Circuits for Low Power ApplicationsVIT-AP University
A large amount of research is currently going on in the field
of reversible logic, which have low heat dissipation, low
power consumption, which is the main factor to apply
reversible in digital VLSI circuit design.This paper introduces
reversible gate named as ‘Inventive0 gate’. The novel gate is
synthesis the efficient adder modules with minimum garbage
output and gate count. The Inventive0 gate capable of
implementing a 4-bit ripple carry adder and carry skip adders.
It is presented that Inventive0 gate is much more efficient and
optimized approach as compared to their existing design, in
terms of gate count, garbage outputs and constant inputs. In
addition, some popular available reversible gates are
implemented in the MOS transistor design the implementation
kept in mind for minimum MOS transistor count and are
completely reversible in behaviour more precise forward and
backward computation. Lesser architectural complexity show
that the novel designs are compact, fast as well as low power.
Area efficient parallel LFSR for cyclic redundancy check IJECEIAES
Cyclic Redundancy Check (CRC), code for error detection finds many applications in the field of digital communication, data storage, control system and data compression. CRC encoding operation is carried out by using a Linear Feedback Shift Register (LFSR). Serial implementation of CRC requires more clock cycles which is equal to data message length plus generator polynomial degree but in parallel implementation of CRC one clock cycle is required if a whole data message is applied at a time. In previous work related to parallel LFSR, hardware complexity of the architecture reduced using a technique named state space transformation. This paper presents detailed explaination of search algorithm implementation and technique to find number of XOR gates required for different CRC algorithms. This paper presents a searching algorithm and new technique to find the number of XOR gates required for different CRC algorithms. The comparison between proposed and previous architectures shows that the number of XOR gates are reduced for CRC algorithms which improve the hardware efficiency. Searching algorithm and all the matrix computations have been performed using MATLAB simulations.
Implementation of Low Power and Area-Efficient Carry Select AdderIJMTST Journal
Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform
fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area
and power consumption in the CSLA. This work uses a simple and efficient gate-level modification to
significantly reduce the area and power of the CSLA. Based on this modification 8-, 16-, 32-,-b square-root
CSLA (SQRT CSLA) architecture have been developed and compared with the regular SQRT CSLA
architecture. The proposed design has reduced area and power as compared with the regular SQRT CSLA
with only a slight increase in the delay. This work evaluates the performance of the proposed designs in
terms of delay, area, power, and their products by hand with logical effort and through custom design and
layout in 0.18-m CMOS process technology. The results analysis shows that the proposed CSLA structure is
better than the regular SQRT CSLA.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
The peer-reviewed International Journal of Engineering Inventions (IJEI) is started with a mission to encourage contribution to research in Science and Technology. Encourage and motivate researchers in challenging areas of Sciences and Technology.
Design and Implementation of Multiplier Using Kcm and Vedic Mathematics by Us...IJMER
International Journal of Modern Engineering Research (IJMER) is Peer reviewed, online Journal. It serves as an international archival forum of scholarly research related to engineering and science education.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
COSA and CSA based 32 -bit unsigned multiplerinventy
In this paper, design of two different arraymultipliers are presented, one by using conditional sum (COSA) logic for addition of partial product terms and another by introducing Carry Save Adder (CSA) in partial product lines. The multipliers presented in this paper were all modeled using VHDL (Very High Speed Integration Hardware Description Language) for 32-bit unsigned data. The comparison is done on the basis of three performanceparameters i.e. Area, Speed and Power consumption. To design an efficient integrated circuit in terms of area, power and speed, has become a challenging task in modern VLSI design field. Previously in the literature, performance analysis was carried out between multiplier using Ripple carry adder (RCA) and by using CLA. In this work, same multiplier is designed by using CSA logic and compare it's performance with the multiplier designed by using CSLA logic. Multiplier with CSA gives better result in terms of speed (78.3% improvement), area (reduced by 4.2%) and power consumption (decreased by 1.4%).
Improved SCTP Scheme To Overcome Congestion Losses Over ManetIJERA Editor
Transmission control conventions have been utilized for data transmission process. TCP has been pre-possessed
for information transmission over wired correspondence having diverse transfer speeds and message delays over
the system. TCP gives correspondence utilizing 3-handshake which sends RTS and ACK originate from server
end and information message has been transmitted over the data transmission gave. This does not give security
over flooding assault happened on the system. TCP gives correspondence between distinctive hubs of the wired
correspondence however when multi-spilling happens in a system TCP does not gives legitimate throughput of
the framework which is significant issue that happened in the past framework. In the proposed work, to beat this
issue SCTP and Improved SCTP transmission control convention has been executed for the framework
execution of the framework. SCTP gives 4-handshake correspondence in the message transmit and improved
SCTP gives the performance when the queue length comes to its full value then it divides the message to other
nodes because of which security element get expansions and this likewise gives correspondence administrations
over multi-spilling and multi-homing. Numerous sender and recipients can impart over wired system utilizing
different methodologies of correspondence through same routers, which debases in the TCP convention. In last
we assess parameters for execution assessment. Here, we composed and actualized our proving ground utilizing
Network Simulator (NS-2.35) to test the execution of both Routing conventions.
Study on the Influence of Ice and Snow on Pavement EvaluationIJERA Editor
The study analyzed mountainous highway operation safety factors from the road environment, traffic environment and climate factors. Utilizing the indoor test to measure the friction coefficient of ice and snow road, summarize the changing trends of friction coefficient which was compared with accident rates, and then establish the model of friction coefficient and accident rate. A model of the vehicle under snow environment was put forward. The study deeply analyzed the influence of snow and ice weather on the roadpavement;it can provide technical support for highway of seasonal frozen area dealing with ice and snow weather.
International Journal of Computational Engineering Research(IJCER) is an intentional online Journal in English monthly publishing journal. This Journal publish original research work that contributes significantly to further the scientific knowledge in engineering and Technology.
Duet advancement of new technology in the field of VLSI and Embedded system, there is an increasing demand of high speed and low power consumption processor. Speed of processor greatly depends on its multiplier as well as adder performance. Due to which high speed adder architecture become important. Sever a ladder architecture designs have been developed to increase the efficiency of the adder. In this paper, we introduce an architecture that performs high speed modified carry select adder using boot hen coder (BEC) Technique. Booth encoder, Mathematics is an ancient Indian system of Mathematics. Here we are introduced two carry select based design. These designs are implementation Xilinx Vertex device family.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
A CORDIC based QR Decomposition Technique for MIMO Detection IJECEIAES
CORDIC based improved real and complex QR Decomposition (QRD) for channel pre-processing operations in (Multiple-Input Multiple-Output) MIMO detectors are presented in this paper. The proposed design utilizes pipelining and parallel processing techniques and reduces the latency and hardware complexity of the module respectively. Computational complexity analysis report shows the superiority of our module by 16% compared to literature. The implementation results reveal that the proposed QRD takes shorter lat ency compared to literature. The power consumption of 2x2 real channel matrix and 2x2 complex channel matrix was found to be 12mW and 44mW respectively on the state-of-the-art Xilinx Virtex 5 FPGA.
Cost Efficient Design of Reversible Adder Circuits for Low Power ApplicationsVIT-AP University
A large amount of research is currently going on in the field
of reversible logic, which have low heat dissipation, low
power consumption, which is the main factor to apply
reversible in digital VLSI circuit design.This paper introduces
reversible gate named as ‘Inventive0 gate’. The novel gate is
synthesis the efficient adder modules with minimum garbage
output and gate count. The Inventive0 gate capable of
implementing a 4-bit ripple carry adder and carry skip adders.
It is presented that Inventive0 gate is much more efficient and
optimized approach as compared to their existing design, in
terms of gate count, garbage outputs and constant inputs. In
addition, some popular available reversible gates are
implemented in the MOS transistor design the implementation
kept in mind for minimum MOS transistor count and are
completely reversible in behaviour more precise forward and
backward computation. Lesser architectural complexity show
that the novel designs are compact, fast as well as low power.
Area efficient parallel LFSR for cyclic redundancy check IJECEIAES
Cyclic Redundancy Check (CRC), code for error detection finds many applications in the field of digital communication, data storage, control system and data compression. CRC encoding operation is carried out by using a Linear Feedback Shift Register (LFSR). Serial implementation of CRC requires more clock cycles which is equal to data message length plus generator polynomial degree but in parallel implementation of CRC one clock cycle is required if a whole data message is applied at a time. In previous work related to parallel LFSR, hardware complexity of the architecture reduced using a technique named state space transformation. This paper presents detailed explaination of search algorithm implementation and technique to find number of XOR gates required for different CRC algorithms. This paper presents a searching algorithm and new technique to find the number of XOR gates required for different CRC algorithms. The comparison between proposed and previous architectures shows that the number of XOR gates are reduced for CRC algorithms which improve the hardware efficiency. Searching algorithm and all the matrix computations have been performed using MATLAB simulations.
Implementation of Low Power and Area-Efficient Carry Select AdderIJMTST Journal
Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform
fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area
and power consumption in the CSLA. This work uses a simple and efficient gate-level modification to
significantly reduce the area and power of the CSLA. Based on this modification 8-, 16-, 32-,-b square-root
CSLA (SQRT CSLA) architecture have been developed and compared with the regular SQRT CSLA
architecture. The proposed design has reduced area and power as compared with the regular SQRT CSLA
with only a slight increase in the delay. This work evaluates the performance of the proposed designs in
terms of delay, area, power, and their products by hand with logical effort and through custom design and
layout in 0.18-m CMOS process technology. The results analysis shows that the proposed CSLA structure is
better than the regular SQRT CSLA.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
The peer-reviewed International Journal of Engineering Inventions (IJEI) is started with a mission to encourage contribution to research in Science and Technology. Encourage and motivate researchers in challenging areas of Sciences and Technology.
Design and Implementation of Multiplier Using Kcm and Vedic Mathematics by Us...IJMER
International Journal of Modern Engineering Research (IJMER) is Peer reviewed, online Journal. It serves as an international archival forum of scholarly research related to engineering and science education.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
COSA and CSA based 32 -bit unsigned multiplerinventy
In this paper, design of two different arraymultipliers are presented, one by using conditional sum (COSA) logic for addition of partial product terms and another by introducing Carry Save Adder (CSA) in partial product lines. The multipliers presented in this paper were all modeled using VHDL (Very High Speed Integration Hardware Description Language) for 32-bit unsigned data. The comparison is done on the basis of three performanceparameters i.e. Area, Speed and Power consumption. To design an efficient integrated circuit in terms of area, power and speed, has become a challenging task in modern VLSI design field. Previously in the literature, performance analysis was carried out between multiplier using Ripple carry adder (RCA) and by using CLA. In this work, same multiplier is designed by using CSA logic and compare it's performance with the multiplier designed by using CSLA logic. Multiplier with CSA gives better result in terms of speed (78.3% improvement), area (reduced by 4.2%) and power consumption (decreased by 1.4%).
Improved SCTP Scheme To Overcome Congestion Losses Over ManetIJERA Editor
Transmission control conventions have been utilized for data transmission process. TCP has been pre-possessed
for information transmission over wired correspondence having diverse transfer speeds and message delays over
the system. TCP gives correspondence utilizing 3-handshake which sends RTS and ACK originate from server
end and information message has been transmitted over the data transmission gave. This does not give security
over flooding assault happened on the system. TCP gives correspondence between distinctive hubs of the wired
correspondence however when multi-spilling happens in a system TCP does not gives legitimate throughput of
the framework which is significant issue that happened in the past framework. In the proposed work, to beat this
issue SCTP and Improved SCTP transmission control convention has been executed for the framework
execution of the framework. SCTP gives 4-handshake correspondence in the message transmit and improved
SCTP gives the performance when the queue length comes to its full value then it divides the message to other
nodes because of which security element get expansions and this likewise gives correspondence administrations
over multi-spilling and multi-homing. Numerous sender and recipients can impart over wired system utilizing
different methodologies of correspondence through same routers, which debases in the TCP convention. In last
we assess parameters for execution assessment. Here, we composed and actualized our proving ground utilizing
Network Simulator (NS-2.35) to test the execution of both Routing conventions.
Study on the Influence of Ice and Snow on Pavement EvaluationIJERA Editor
The study analyzed mountainous highway operation safety factors from the road environment, traffic environment and climate factors. Utilizing the indoor test to measure the friction coefficient of ice and snow road, summarize the changing trends of friction coefficient which was compared with accident rates, and then establish the model of friction coefficient and accident rate. A model of the vehicle under snow environment was put forward. The study deeply analyzed the influence of snow and ice weather on the roadpavement;it can provide technical support for highway of seasonal frozen area dealing with ice and snow weather.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Localized Algorithm for Channel Assignment in Cognitive Radio NetworksIJERA Editor
Cognitive Radio has been emerged as a revolutionary solution to migrate the current shortage of spectrum
allocation in wireless networks. In this paper, an improved localized channel allocation algorithm based on
channel weight is proposed. A factor of channel stability is introduced based on link environment, which
efficiently assigns the best channels to the links. Based on the framework, a conflict resolution strategy is used to
make the scheme adaptable to different network conditions. Calculations indicate that this algorithm can reduce
the conflicts, increase the delivery rate and link assignment rate compared with the basic channel assignment
algorithm.
Modified Sierpinski Gasket for Wi-Fi and WLAN ApplicationsIJERA Editor
The hasty growth of wireless technologies has drawn new demands for integrated components including antennas and antenna on chip is a new mantra in the area of antenna research. Various techniques have been suggested by researchers for the miniaturization of microstrip patch antennas with multiband characteristics. Numerous antennas for multiband operation have been studied and designed for communication and radar systems. One of the solutions for the multiband characteristics is the fractal antenna. The Fractal antennas are based on the concept of fractal geometries. They can be designed in a variety of shapes in order to obtain enhanced gain and bandwidth, dual band and circular polarization to even ultra-wideband operation. In this paper, the fractal antenna has been designed using the Arlon substrate with relative permittivity of 1.3 and a substrate of Sierpinski gasket shaped placed on it. Feed used is the line feed. The designed antenna is a low profile, small size and multiband antenna since it can be operated at different frequencies within the frequency range of (1.75 – 2.65) and (5.7 – 7.65) GHz. It includes the frequencies used for wireless WLAN application and used to receive and transmit a high-frequency signal.
An efficient model for design of 64-bit High Speed Parallel Prefix VLSI adderIJMER
International Journal of Modern Engineering Research (IJMER) is Peer reviewed, online Journal. It serves as an international archival forum of scholarly research related to engineering and science education.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Design of High Speed 128 bit Parallel Prefix AddersIJERA Editor
In this paper, we propose 128-bit Kogge-Stone, Ladner-Fischer, Spanning tree parallel prefix adders and
compared with Ripple carry adder. In general N-bit adders like Ripple Carry Adders (slow adders compare to
other adders), and Carry Look Ahead adders (area consuming adders) are used in earlier days. But now the most
Industries are using parallel prefix adders because of their advantages compare to other adders. Parallel prefix
adders are faster and area efficient. Parallel prefix adder is a technique for increasing the speed in DSP processor
while performing addition. While when we want to design any 128-bit operating systems and processors we can
use these adders in place of regular adders. We simulate and synthesis different types of 128-bit prefix adders
using Xilinx ISE 12.3 tool. By using these synthesis results, we noted the performance parameters like number
of LUTs and delay. We compare these three adders in terms of LUTs (represents area) and delay values.
— Parallel Prefix adders have been one of the most
notable among several designs proposed in the past. The
advantage of utilizing the flexibility in implementing these
structures based upon through put requirements. Due to
continuing integrating intensity and the growing needs of
portable devices, low power and high performance designs are of
prime importance. The classical parallel prefix adder structures
presented in the literature over the years optimize for logic depth,
area, and fan-out and interconnect count of logic circuits. In this
proposed system, Kogge-Stone adder which is one of types of
parallel prefix adder is used. Kogge stone is the fastest adder
because of its minimum fan-out. When parallel prefix adder is
compared with classical adders it is advantageous in every aspect.
The study reveals that Parallel Prefix adder has the least power
delay product when compared with its peer existing adder
structures (Ripple carry adder, Carry save adders etc).
Simulation results are verified using Xilinx 10.1 and
MODELSIM 6.4a softwares.
Area Delay Power Efficient and Implementation of Modified Square-Root Carry S...IJTET Journal
Abstract: In VLSI Technology, Carry Propagation Delay is the most important concern for the Adders. Adder is the most unavoidable component for the arithmetic performances. This paper is Modified Square Root-Carry Select Adder (SQRT-CSLA) design reduces the delay with 16 bit adder. Carry select adder have two units for Carry Generation (CG) and Carry Selection (CS). The modified SQRT-CSLA design can gives parallel path for carry propagation. So the overall adder delay has reduced. Modified design is obtained using Ripple Carry Adder (RCA) with Boolean Excess-1 Converter (BEC). BEC produces an output i.e., is an excess one result for given input bits. Then input bits and BEC output is given to multiplexer for carry selection. Use of BEC instead of dual RCA gives efficient carry propagation delay and it consumes the lower power and overall gates using in design is reduced with compared to carry select adder with dual RCA. The final sum is calculated using final sum generation.
Area, Delay and Power Comparison of Adder TopologiesVLSICS Design
Adders form an almost obligatory component of every contemporary integrated circuit. The prerequisite of the adder is that it is primarily fast and secondarily efficient in terms of power consumption and chip area. This paper presents the pertinent choice for selecting the adder topology with the tradeoff between delay, power consumption and area. The adder topology used in this work are ripple carry adder, carry lookahead adder, carry skip adder, carry select adder, carry increment adder, carry save adder and carry bypass adder. The module functionality and performance issues like area, power dissipation and propagation delay are analyzed at 0.12µm 6metal layer CMOS technology using microwind tool.
Design Analysis of Delay Register with PTL Logic using 90 nm TechnologyIJEEE
This paper presents low area and power efficient delay register using CMOS transistors. The proposed register has reduced area than the conventional register. This resistor design consists of 6 NMOS and 6 PMOS. The proposed delay register has been designed in logic editor and simulated using 90nm technology. Also the layout simulation and parametric analysis has been done to find out the results. In this paper register has been designed using full automatic layout design and semicustom layout design. Then the performance of these different designs has been analyzed and compared in terms of power, delay and area. The simulation result shows that circuit design of delay register using PTL techniques improved by power 0.05% and 61.8% area.
Design of 32 bit Parallel Prefix Adders IOSR Journals
In this paper, we propose 32 bit Kogge-Stone, Brent-Kung, Ladner-Fischer parallel prefix adders. In
general N-bit adders like Ripple Carry Adders (slow adders compare to other adders), and Carry Look Ahead
adders (area consuming adders) are used in earlier days. But now the most Industries are using parallel prefix
adders because of their advantages compare to other adders. Parallel prefix adders are faster and area
efficient. Parallel prefix adder is a technique for increasing the speed in DSP processor while performing
addition. We simulate and synthesis different types of 32-bit prefix adders using Xilinx ISE 10.1i tool. By using
these synthesis results, we noted the performance parameters like number of LUTs and delay. We compare these three adders in terms of LUTs (represents area) and delay values.
Design of 32 bit Parallel Prefix AddersIOSR Journals
Abstract: In this paper, we propose 32 bit Kogge-Stone, Brent-Kung, Ladner-Fischer parallel prefix adders. In general N-bit adders like Ripple Carry Adders (slow adders compare to other adders), and Carry Look Ahead adders (area consuming adders) are used in earlier days. But now the most Industries are using parallel prefix adders because of their advantages compare to other adders. Parallel prefix adders are faster and area efficient. Parallel prefix adder is a technique for increasing the speed in DSP processor while performing addition. We simulate and synthesis different types of 32-bit prefix adders using Xilinx ISE 10.1i tool. By using these synthesis results, we noted the performance parameters like number of LUTs and delay. We compare these three adders in terms of LUTs (represents area) and delay values. Keywords− prefix adder, carry operator, Kogge-Stone, Brent-Kung, Ladner-Fischer
Addition is a fundamental arithmetic operation and acts as a building block for synthesizing of all other operations. A high-performance adder is one of the key components in the design of Application Specific Integrated Circuits (ASIC). In this work, three low power full adders are designed with full swing AND, OR and XOR gates to reduce threshold voltage problem which is commonly encountered in Gate Diffusion Input (GDI) logic. This problem usually does not allow the full adder circuits to operate without additional inverters. However, the three full adders are successfully realized using full swing gates with the significant improvement in their performance. The performance of the proposed design is simulated through SPICE simulations using 45 nm technology models.
Efficient Design of Reversible Multiplexers with Low Quantum CostIJERA Editor
Multiplexing is the generic term used to designate the operation of sending one or more analogue or digital
signals over a common transmission line at dissimilar times or speeds and as such, the scheme we use to do just
that is called a Multiplexer. In digital electronics, multiplexers are similarly known as data selectors as they can
“select” each input line, are made from individual Analogue Switches encased in a single IC package as
conflicting to the “mechanical” type selectors such as standard conservative switches and relays. In today era,
reversibility has become essential part of digital world to make digital circuits more efficient. In this paper, we
have proposed a new method to reduce quantum cost and power for various multiplexers. The results are
simulated in Xilinx by using VHDL language.
Overview of the fundamental roles in Hydropower generation and the components involved in wider Electrical Engineering.
This paper presents the design and construction of hydroelectric dams from the hydrologist’s survey of the valley before construction, all aspects and involved disciplines, fluid dynamics, structural engineering, generation and mains frequency regulation to the very transmission of power through the network in the United Kingdom.
Author: Robbie Edward Sayers
Collaborators and co editors: Charlie Sims and Connor Healey.
(C) 2024 Robbie E. Sayers
Quality defects in TMT Bars, Possible causes and Potential Solutions.PrashantGoswami42
Maintaining high-quality standards in the production of TMT bars is crucial for ensuring structural integrity in construction. Addressing common defects through careful monitoring, standardized processes, and advanced technology can significantly improve the quality of TMT bars. Continuous training and adherence to quality control measures will also play a pivotal role in minimizing these defects.
Vaccine management system project report documentation..pdfKamal Acharya
The Division of Vaccine and Immunization is facing increasing difficulty monitoring vaccines and other commodities distribution once they have been distributed from the national stores. With the introduction of new vaccines, more challenges have been anticipated with this additions posing serious threat to the already over strained vaccine supply chain system in Kenya.
Forklift Classes Overview by Intella PartsIntella Parts
Discover the different forklift classes and their specific applications. Learn how to choose the right forklift for your needs to ensure safety, efficiency, and compliance in your operations.
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COLLEGE BUS MANAGEMENT SYSTEM PROJECT REPORT.pdfKamal Acharya
The College Bus Management system is completely developed by Visual Basic .NET Version. The application is connect with most secured database language MS SQL Server. The application is develop by using best combination of front-end and back-end languages. The application is totally design like flat user interface. This flat user interface is more attractive user interface in 2017. The application is gives more important to the system functionality. The application is to manage the student’s details, driver’s details, bus details, bus route details, bus fees details and more. The application has only one unit for admin. The admin can manage the entire application. The admin can login into the application by using username and password of the admin. The application is develop for big and small colleges. It is more user friendly for non-computer person. Even they can easily learn how to manage the application within hours. The application is more secure by the admin. The system will give an effective output for the VB.Net and SQL Server given as input to the system. The compiled java program given as input to the system, after scanning the program will generate different reports. The application generates the report for users. The admin can view and download the report of the data. The application deliver the excel format reports. Because, excel formatted reports is very easy to understand the income and expense of the college bus. This application is mainly develop for windows operating system users. In 2017, 73% of people enterprises are using windows operating system. So the application will easily install for all the windows operating system users. The application-developed size is very low. The application consumes very low space in disk. Therefore, the user can allocate very minimum local disk space for this application.
Explore the innovative world of trenchless pipe repair with our comprehensive guide, "The Benefits and Techniques of Trenchless Pipe Repair." This document delves into the modern methods of repairing underground pipes without the need for extensive excavation, highlighting the numerous advantages and the latest techniques used in the industry.
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Saudi Arabia stands as a titan in the global energy landscape, renowned for its abundant oil and gas resources. It's the largest exporter of petroleum and holds some of the world's most significant reserves. Let's delve into the top 10 oil and gas projects shaping Saudi Arabia's energy future in 2024.
Welcome to WIPAC Monthly the magazine brought to you by the LinkedIn Group Water Industry Process Automation & Control.
In this month's edition, along with this month's industry news to celebrate the 13 years since the group was created we have articles including
A case study of the used of Advanced Process Control at the Wastewater Treatment works at Lleida in Spain
A look back on an article on smart wastewater networks in order to see how the industry has measured up in the interim around the adoption of Digital Transformation in the Water Industry.
Water scarcity is the lack of fresh water resources to meet the standard water demand. There are two type of water scarcity. One is physical. The other is economic water scarcity.
1. MUX Int. Journal of Engineering Research and Applications www.ijera.com
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Design the High Speed Kogge-Stone Adder by Using
MUX
Vishal Galphat, Nitin Lonbale ECE Deptt, SBITM, Betul, M.P.
Abstract
In this Technical era the high speed and low area of VLSI chip are very- very essential factors. Day by day
number of transistors and other active and passive elements are growing on VLSI chip. In Integral part of the
processor adders play an important role. In this paper we are using proposed kogge-stone adders for binary
addition to reduce the size and increase the efficiency or processors speed. Proposing kogge stone adder
provides less components, less path delay and better speed compare to other existing kogge stone adder and
other adders. Here we are comparing the kogge stone adders of different-different word size from other adders.
The design and experiment can be done by the aid of Xilinx 14.1i Spartan 3 device family.
Keywords: Kogge Stone Adder, Ripple Carry Adder, Proposed Kogge Stone Adder, 14.1i Spartan 3
Device Family.
I. INTRODUCTION
The stage of multiplication in any crucial appli-cation
considered greatly influence the processor speed. The
processors speed mostly depends on adder design
techniques. Adder is the device by which two or
more than two bit information can be added. These
devices are need of hour for dig-ital signal processing
and image signal processing. Vedic mathematics is
the best option to calculate the fast asthmatics and
logical operation in fast way. There are 16 sutras in
vedic mathematics like urd-hawa triyakbhayam,
Nikhilam etc. So we are kept in mind that reduce the
area and logical path delay as possible as. The
propagation delay is played a very important role for
digital signal processing, image processing and other
various suitable appli-cation..The shorter the
propagation delay, the higher the speed of the circuit
and vice-versa. Propagation delay should be
minimizing as possible as, for high efficient addition.
For better explanation we can take instance for N bit
addition in which generally propagation delay is
occurred highly. When we add one high bit
information(A0; A1; A2; A3) to another high bit
information(B0; B1; B2; B3), carry bit(C0; C1; C2;
C3) is occurred due to normally binary addition
operation. This carry propagates to next bit and now
bit addition is performed by 3 bit adder. So carry will
propagate to the next bit over and over, this cause
propagation delay will be occurred. We have
principal component for 2 and 3 bit addition such as
half and full adder. There another serial and parallel
adder to design fast processing adder like
compressor, Ripple carry adder, look a head adder
etc.
Fig. 1. A Propagation delay for bit binary addition
II. OBJECTIVE
The bottleneck motive the work is to design and
implement a high speed adder. Which can be used in
any processor based application. Here we are
proposing a Kogge stone adder (KSA) by using
MUX to reduce the propagation delay.
Fig. 2. A MUX blockdiagram for working as a
XOR gate
III. MUX AS A XOR GATE
XOR gate is the special type of gate which is
represented by plus sign with encirclement. The
RESEARCH ARTICLE OPEN ACCESS
2. MUX Int. Journal of Engineering Research and Applications www.ijera.com
ISSN: 2248-9622, Vol. 5, Issue 8, (Part - 2) August 2015, pp.58-60
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matter of complexity can be reduced by the aid of
designing of the gates. Less number of gates provides
the less area for attractive designing in digital
processing. Xor gate is comprised with five gates
(Two AND, two NOT and one OR gate). XOR gate
can also be replaced by Multiplexer (MUX). In
digital electronics we are having two types of
universal gates like NAND and NOR gate. By using
any universal gate we can design any type of gate.
Likewise MUX behaves like as universal gate that
means by using mux any type of gate can be
designed. To design the 2 inputs XOR gate one input
of MUX must be invert to the other and both input
would be connected together. Another input of XOR
gate would be applied to the select line of the MUX.
So, the output of the MUX would be as same as
the output of XOR Gate. The advantage of this type
of designing that is Differential Cascode Voltage
Switch Logic (DCVSL) as a MUX is that it produces
both true and complementary outputs when provided
with true and complementary inputs.
IV. DIFFERENTIAL CASCODE
VOLTAGE SWITCH LOGIC (RCA)
A ripple carry adder is a parallel digital adder
circuit that produces the arithmetic sum of two binary
numbers. It can be comprised with full adders
connected in cascaded, with the carry output from
each full adder connected to the carry input of the
next full adder in the chain. This kind of adder is
typically known as Ripple Carry Adder because carry
ripples to next full adder. The layout of Ripple Carry
Adder is simple, which allows fast design
Fig. 3. A Functional Diagram of Ripple Carry
Adder
time. The Ripple Carry Adder is slowest among all
the adders because every full adder must wait till the
previous full adder generates the carry bit for its
input.
S0 = A0B0Cin (1)
C0 = (A0B0) + (B0Cin) + (CinA0) (2)
S1 = A1B1C0 (3)
C1 = (A1B1) + (B1C0) + (C0A1) (4)
S2 = A2B2C1 (5)
C2= (A2B2) + (B2C1) + (C1A2) (6)
Sn = AnBnCn 1 (7)
Cn = (An Bn) + (Bn Cn 1) + (Cn 1An) (8)
The ripple carry adder has the smallest are when
compare to other adder. it is limited to application
where the area and propagation delay must be
minimized. As we can see in diagram of ripple carry
adder which has much more number of gates. Ripple
carry adder does not provide efficient area and speed
because of its complexity.
Fig. 4. A Basic Building Block of KSA
Fig. 5. Proposed KSA by using MUX
V. KOGGE-STONE ADDER
The Kogge-Stone adder concept was developed
by Peter M. Kogge and Harold S. Stone, which they
published in 1973 in a seminal paper titled. KS adder
is the special and fast adder. Kogge stone adder is
comprised with three units such as pre processing,
carry generator and post processing unit.
P = AiBi (9)
G = AiBi (10)
Ci = Gi (11)
Si = PiCi 1 (12)
3. MUX Int. Journal of Engineering Research and Applications www.ijera.com
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In kogge stone adder XOR can be replaced by
MUX which provide different structure and gives the
true and complement value at a time.
TABLE I
COMPRESION OF DIFFERENT TYPES OF
ADDER WITH KSA BY MUX
Bit size Adder Area Delay in ns
8 bit Regular(RCA) 144 11.92
SQRT BEC 132 13.69
CSLA Modified (CBL) 111 11.15
KSA by MUX 83 5.776
16 bit Regular (RCA) 348 16.15
SQRT BEC 291 18.77
CSLA Modified (CBL) 276 15.48
KSA by MUX 166 12.85
32 bit Regular (RCA) 698 28.97
SQRT BEC 762 34.44
CSLA Modified (CBL) 552 26.23
KSA by MUX 332 24.56
64 bit Regular (RCA) 1592 52.82
SQRT BEC 1498 64.61
CSLA Modified (CBL) 1104 47.74
KSA by MUX 664 45.25
VI. CONCLUSION AND FUTURE
WORK
Eventually a novel high speed adder can be
implemented by different structure of kogge stone
adder. Simulation result is implementing on Xilinx
14.2i Spartan 3E advanced VHDL software tool. This
experiment gives better result than other adder apart
from that it gives less area and low propagation
delay. In future this adder can be helped to design a
high speed multiplier which is essential for digital
processor. Apart from that these fast adder and
multiplier can be used for convolution and de-
convolution.
REFERENCES
[1] Youngjoon Kim and Lee-Sup Kim, 2001.A
low power carry select adder with reduced
area,IEEE International Symposium on
Circuits and Systems, vol.4, pp.218-221.
[2] Akhilesh Tyagi,1990.A Reduced Area
Scheme for Carry- Se-lect Adders,IEEE
International Conference on Computer
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[3] Belle W.Y.Wei and Clark
D.Thompson,1990.Area-Time Optimal
Adder Design, IEEE transactions on
Computers, vol.39, pp. 666-675.
[4] Kogge P and Stone H, 1973.A Parallel
Algorithm for the Efficient Solution of a
General Class of Recurrence Relations,
IEEE Transactions on Computers, Vol. C-
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[5] Madhu Thakur and Javed Ashraf,
2012.Design of Braun Mul-tiplier with
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on FPGAInternational Journal of Scientific
and Engineering Re-search, Vol. 3, No. 10,
pp. 03-06, ISSN 2229-5518.
[6] Somayeh Babazadeh and Majid Haghparast,
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Reversible Multiplier Circuit, Journal of
Basic and Applied Scientific Research.
[7] Sumeer Goel, Mohammed A. Elgamel,
Magdy A. Bay-oumi, Yasser Hanafy,
2006.Design Methodologies for High-
Performance Noise-Tolerant XOR-XNOR
Circuits,IEEE Transac-tions on Circuits and
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[8] Mohammad Shamim Imtiaz, Md Abdul Aziz
Suzon, Mahmudur Rahman,2012.Design of
Energy efficient Full adder using hybrid
CMOS logic styleInternational Journal of
Advances in Engineer-ing and Technology,
Jan 2012.
[9] Ila Gupta, Neha Arora, Prof. B.P. Singh,
2012.Analysis of Several 2:1 Multiplexer
Circuits at 90nm and 45nm Technolo-
gies,International Journal of Scientific and
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February 2012.