This document analyzes delays in current mode threshold logic gate designs. It proposes a new implementation of current mode threshold functions that improves gate delay and switching energy. Simulation results using the Tanner tool show that gates implemented with the optimum sensor size using the proposed method outperform existing implementations in delay and switching energy.
A customized workflow for indoor CBRN dispersions analysis in subway stationsFLUIDIAN
We use open-source components (Code_Saturne, Salome, Paraview) to develop an automatic CFD workflow that can simulate gas and aerosols dispersion in critical infrastructures such as train and subway stations, hospitals, parkings, commercial centers, etc. It allows to improve alerts and counter-measures devices through virtual sensors of different technology.
Predicting phase durations of traffic lights using live open traffic lights dataBrecht Van de Vyvere
Paper: https://brechtvdv.github.io/Article-Predicting-traffic-light-phases/
Dynamic traffic lights change their current phase duration according to the situation on the intersection, such as crowdedness. In Flanders, only the minimum and maximum duration of the current phase is published. When route planners want to reuse this data they have to predict how long the current phase will take in order to route over these traffic lights. We tested for a live Open Traffic Lights dataset of Antwerp how frequency distributions of phase durations (i) can be used to predict the duration of the current phase and (ii) can be generated client-side on-the-fly with a demonstrator. An overall mean average error (MAE) of 5.1 seconds is reached by using the median for predictions. A distribution is created for every day with time slots of 20 minutes. This result is better than expected, because phase durations can range between a few seconds and over two minutes. When taking the remaining time until phase change into account, we see a MAE around 10 seconds when the remaining time is less than a minute which we still deem valuable for route planning. Unfortunately, the MAE grows linear for phases longer than a minute making our prediction method useless when this occurs. Based on these results, we wish to present two discussion points during the workshop.
Accelerating economics: how GPUs can save you time and moneyLaurent Oberholzer
Graphics processing units - or GPUs as they are more commonly known - are specialized circuits historically designed to efficiently handle computer graphics. They are highly parallel computers which can process large amounts of data simultaneously. The graphics algorithms for which GPUs have been designed and optimized share characteristics with other algorithms used in high-performance computing. For certain well-suited scientific applications, the GPU's infrastructure has been shown to achieve substantial speedups. For example, the evaluation of the Black-Scholes partial differential equation to price financial options has been found to be performed nearly 200 times faster in parallel on a GPU than serially on a single-core CPU (Buck 2006, “GeForce 8800 & NVIDIA CUDA: A New Architecture for Computing on the GPU”).
The main goal of this study is to illustrate how hybrid CPU/GPU systems can be used within computational economics to decrease the execution time of an implementation of a particular model. We start with a mainstream implementation of Raberto et al.'s (2001) Genoa Articial Stock Market ("GASM"), an agent-based model which simulates a financial market in discrete time in which heterogeneous agents trade a single asset. In order to ensure that it is well-suited for execution on the GPU, the algorithm used to clear the market according to the authors' specified mechanism is given a particular attention. Existing parallel programming interfaces - in particular the OpenACC standard and Thrust parallel algorithms library - are then deployed in the code. We aim to show:
- how the codebase of our GASM implementation is adapted to utilize these technologies;
- how incrementally offloading work to the GPU affects the execution time of our model;
- how this speedup varies as a function of the problem size (e.g. number of agents, number of time steps, etc.), i.e. weak scaling; and
- how parameterizing the work distribution within the OpenACC programming model to increase the number of execution units used impacts this speedup, i.e. strong scaling.
This study also aims at giving the reader a working knowledge of GPU-based parallel computing, and when and how it should be used.
VLSI Projects for M. Tech, VLSI Projects in Vijayanagar, VLSI Projects in Bangalore, M. Tech Projects in Vijayanagar, M. Tech Projects in Bangalore, VLSI IEEE projects in Bangalore, IEEE 2015 VLSI Projects, FPGA and Xilinx Projects, FPGA and Xilinx Projects in Bangalore, FPGA and Xilinx Projects in Vijayangar
A customized workflow for indoor CBRN dispersions analysis in subway stationsFLUIDIAN
We use open-source components (Code_Saturne, Salome, Paraview) to develop an automatic CFD workflow that can simulate gas and aerosols dispersion in critical infrastructures such as train and subway stations, hospitals, parkings, commercial centers, etc. It allows to improve alerts and counter-measures devices through virtual sensors of different technology.
Predicting phase durations of traffic lights using live open traffic lights dataBrecht Van de Vyvere
Paper: https://brechtvdv.github.io/Article-Predicting-traffic-light-phases/
Dynamic traffic lights change their current phase duration according to the situation on the intersection, such as crowdedness. In Flanders, only the minimum and maximum duration of the current phase is published. When route planners want to reuse this data they have to predict how long the current phase will take in order to route over these traffic lights. We tested for a live Open Traffic Lights dataset of Antwerp how frequency distributions of phase durations (i) can be used to predict the duration of the current phase and (ii) can be generated client-side on-the-fly with a demonstrator. An overall mean average error (MAE) of 5.1 seconds is reached by using the median for predictions. A distribution is created for every day with time slots of 20 minutes. This result is better than expected, because phase durations can range between a few seconds and over two minutes. When taking the remaining time until phase change into account, we see a MAE around 10 seconds when the remaining time is less than a minute which we still deem valuable for route planning. Unfortunately, the MAE grows linear for phases longer than a minute making our prediction method useless when this occurs. Based on these results, we wish to present two discussion points during the workshop.
Accelerating economics: how GPUs can save you time and moneyLaurent Oberholzer
Graphics processing units - or GPUs as they are more commonly known - are specialized circuits historically designed to efficiently handle computer graphics. They are highly parallel computers which can process large amounts of data simultaneously. The graphics algorithms for which GPUs have been designed and optimized share characteristics with other algorithms used in high-performance computing. For certain well-suited scientific applications, the GPU's infrastructure has been shown to achieve substantial speedups. For example, the evaluation of the Black-Scholes partial differential equation to price financial options has been found to be performed nearly 200 times faster in parallel on a GPU than serially on a single-core CPU (Buck 2006, “GeForce 8800 & NVIDIA CUDA: A New Architecture for Computing on the GPU”).
The main goal of this study is to illustrate how hybrid CPU/GPU systems can be used within computational economics to decrease the execution time of an implementation of a particular model. We start with a mainstream implementation of Raberto et al.'s (2001) Genoa Articial Stock Market ("GASM"), an agent-based model which simulates a financial market in discrete time in which heterogeneous agents trade a single asset. In order to ensure that it is well-suited for execution on the GPU, the algorithm used to clear the market according to the authors' specified mechanism is given a particular attention. Existing parallel programming interfaces - in particular the OpenACC standard and Thrust parallel algorithms library - are then deployed in the code. We aim to show:
- how the codebase of our GASM implementation is adapted to utilize these technologies;
- how incrementally offloading work to the GPU affects the execution time of our model;
- how this speedup varies as a function of the problem size (e.g. number of agents, number of time steps, etc.), i.e. weak scaling; and
- how parameterizing the work distribution within the OpenACC programming model to increase the number of execution units used impacts this speedup, i.e. strong scaling.
This study also aims at giving the reader a working knowledge of GPU-based parallel computing, and when and how it should be used.
VLSI Projects for M. Tech, VLSI Projects in Vijayanagar, VLSI Projects in Bangalore, M. Tech Projects in Vijayanagar, M. Tech Projects in Bangalore, VLSI IEEE projects in Bangalore, IEEE 2015 VLSI Projects, FPGA and Xilinx Projects, FPGA and Xilinx Projects in Bangalore, FPGA and Xilinx Projects in Vijayangar
Implementation of pull up pull-down network for energy optimization in full a...IJARIIT
Nowadays the requirements of energy optimized low power circuits in higher-end applications such as
communication, IoT, biomedical systems etc., there are several techniques used to implement energy optimization in low power
circuits but the static power dissipation need to improve such kind of circuits. The conventional topology has been
implemented in basic logical gates but the delay and power much higher in each individual cell. Now we proposed an
unbalanced pull-up and pull-down network in full adder circuit using symbols. These techniques were employed to reduce the
static power dissipation and switching delay in each individual cell. The design was implemented in Cadence virtuoso TMSC
180nm CMOS technology and it’s obtaining the total power dissipation 5.128nW.The pull-up and pull-down network used to
reduce the static power dissipation in full adder is used to improve the operating speed of each individual.
Low Power Design of Standard Digital Gate Design Using Novel Sleep Transisto...IJMER
In the nanometer range design technologies static power consumption is very important
issue in present peripheral devices. In the CMOS based VLSI circuits technology is scaling towards
down in respect of size and achieving higher operating speeds. We have also considered these
parameters such that we can control the leakage power. As process model design are getting smaller
the density of device increases and threshold voltage as well as oxide thickness decrease to maintain
the device performance. In this article two novel circuit techniques for reduction leakage current in
NAND and NOR inverters using novel sleepy and sleepy property are investigated. We have proposed a
design model that has significant reduction in power dissipation during inactive (standby) mode of
operation compared to classical power gating methods for these circuit techniques. The proposed
circuit techniques are applied to NAND and NOR inverters and the results are compared with earlier
inverter leakage minimization techniques. All low leakage models of inverters are designed and
simulated in Tanner Tool environment using 65 nm CMOS Technology (1volt) technologies. Average
power, Leakage power, sleep transistor
Area efficient fixed-width squarer with dynamic error-compensation circuitLogicMindtech Nologies
VLSI Projects for M. Tech, VLSI Projects in Vijayanagar, VLSI Projects in Bangalore, M. Tech Projects in Vijayanagar, M. Tech Projects in Bangalore, VLSI IEEE projects in Bangalore, IEEE 2015 VLSI Projects, FPGA and Xilinx Projects, FPGA and Xilinx Projects in Bangalore, FPGA and Xilinx Projects in Vijayangar
A new method for self-organized dynamic delay loop associated pipeline with ...IJECEIAES
The minimization of propagation delay between pipeline stages is very important in wave propagation through pipeline-stages. The propagation delay can be minimized by minimizing the number of stages in a pipeline. In the proposed design a dynamic stage control is imparted in the pipeline. The propagation delay can be optimized in any type of pipeline by controlling number of stages dynamically. The pipeline interpretation helps a lot to overcome the flaws due to not ready sequence (NRS) and synchronization problems. It is observed that, in the pipeline design the basic and actively involved pipeline techniques are concerned with different challenges like clock, throughput, cell area, and sizes. As the data throughput increases the number of stages in pipeline also needs to be increased to meet the desired goal. In the case of unpredictable data speed, the definite number of pipeline stages creates severe problems. In this work a dynamic pipeline is integrated where the number of stages is dynamically changing depending up on data speed. In dynamic pipeline technique the circuit cell area of reconfigurable computing system (RCS) will be reduced dynamically at low-speed data transmission. In the high-speed data communication, the data speed is managed and controlled by dynamic delay loops.
In this paper a CMOS AND gate layout has been designed and simulated using 90nm technology. The layout has been designed using two approaches, namely fully automatic and semicustom. In fully automatic technique AND gate schematic is developed which is constructed into its equivalent spice file for the automatic layout generation. In semicustom technique layout has been developed mainly to optimize area and power. It can be observed from the simulated results that semicustom layout results in 11.2µm2 area consumption by consuming almost the same power as compared to fully automatic design.
Current Comparison Domino based CHSK Domino Logic Technique for Rapid Progres...IJECEIAES
The proposed domino logic is developed with the combination of Current Comparison Domino (CCD) logic and Conditional High Speed Keeper (CHSK) domino logic. In order to improve the performance metrics like power, delay and noise immunity, the redesign of CHSK is proposed with the CCD. The performance improvement is based on the parasitic capacitance, which reduces on the dynamic node for robust and rapid process of the circuit. The proposed domino logic is designed with keeper and without keeper to measure the performance metrics of the circuit. The outcomes of the proposed domino logic are better when compared to the existing domino logic circuits. The simulation of the proposed CHSK based on the CCD logic circuit is carried out in Cadence Virtuoso tool.
Nexgen Technology Address:
Nexgen Technology
No :66,4th cross,Venkata nagar,
Near SBI ATM,
Puducherry.
Email Id: praveen@nexgenproject.com.
www.nexgenproject.com
Mobile: 9751442511,9791938249
Telephone: 0413-2211159.
NEXGEN TECHNOLOGY as an efficient Software Training Center located at Pondicherry with IT Training on IEEE Projects in Android,IEEE IT B.Tech Student Projects, Android Projects Training with Placements Pondicherry, IEEE projects in pondicherry, final IEEE Projects in Pondicherry , MCA, BTech, BCA Projects in Pondicherry, Bulk IEEE PROJECTS IN Pondicherry.So far we have reached almost all engineering colleges located in Pondicherry and around 90km
Nexgen Technology Address:
Nexgen Technology
No :66,4th cross,Venkata nagar,
Near SBI ATM,
Puducherry.
Email Id: praveen@nexgenproject.com.
www.nexgenproject.com
Mobile: 9751442511,9791938249
Telephone: 0413-2211159.
NEXGEN TECHNOLOGY as an efficient Software Training Center located at Pondicherry with IT Training on IEEE Projects in Android,IEEE IT B.Tech Student Projects, Android Projects Training with Placements Pondicherry, IEEE projects in pondicherry, final IEEE Projects in Pondicherry , MCA, BTech, BCA Projects in Pondicherry, Bulk IEEE PROJECTS IN Pondicherry.So far we have reached almost all engineering colleges located in Pondicherry and around 90km
A verilog based simulation methodology for estimating statistical test for th...ijsrd.com
The low Power estimation is an important aspect in digital VLSI circuit design. The estimation includes a power dissipation of a circuit and hence this to be reduces. The power estimations are specific to a particular component of power. The process of optimization of circuits for low power, user should know the effects of design techniques on each component. There are different power dissipation methods for reduction in power component. In this paper, estimating the power like short circuit and the total power, power reduction technique and the application of different proposed technique has been presented here. Hence, it is necessary to provide the information about the effect on each of these components.
Extremely Low Power FIR Filter for a Smart Dust Sensor ModuleCSCJournals
Digital filters are common components in many applications today, also in for sensor systems, such as large-scale distributed smart dust sensors. For these applications the power consumption is very critical, it has to be extremely low. With the transistor technology scaling becoming more and more sensitive to e.g. gate leakage, it has become a necessity to find ways to minimize the flow of leakage in current CMOS logic. This paper studies sub-threshold source coupled logic (STSCL) in a 45-nm process. The STSCL can be used instead of traditional CMOS to meet the low power and energy consumption requirements. The STSCL style is in this paper used to design a digital filter, applicable for the audio interface of a smart dust sensor where the sample frequency will be 44.1 kHz. A finite-length impulse response (FIR) filter is used with transposed direct form structure and for the coefficient multiplication five-bit canonic signed digit [7] based serial/parallel multipliers were used. The power consumption is calculated along with the delay in order to present the power delay product (PDP) such that the performance of the sub-threshold logic can be compared with corresponding CMOS implementation. The simulated results shows a significant reduction in energy consumption (in terms of PDP) with the system running at a supply voltage as low as 0.2 V using STSCL.
An Ultra-Low Power Robust Koggestone Adder at Sub-Threshold Voltages for Impl...VLSICS Design
The growing demand for energy constrained applications and portable devices have created a dire need for ultra-low power circuits. Implantable biomedical devices such as pacemakers need ultra-low power circuits for a better battery life for uninterrupted biomedical data processing. Circuits operating in subthreshold region minimize the energy per operation, thus providing a better platform for energy constrained implantable biomedical devices. This paper presents 8, 16 and 32-bit ultra-low power robust Kogge-Stone adders with improved performance. These adders operate at subthreshold supply voltages which can be used for low power implantable bio-medical devices such as pacemakers. To improve the performance of these adders in sub-threshold region, forward body bias technique and multi-threshold transistors are used. The adders are designed using NCSU 45nm bulk CMOS process library and the simulations were performed using HSPICE circuit simulator. Quantitative power-performance analysis is performed at slow-slow (SS), typical-typical (TT) and fast-fast (FF) corners clocked at 50 KHz for temperature ranging from 25̊C to 120̊C. For a supply voltage 0.3V, all the adders had the least PDP. Using 0.3V as the supply voltage, multi threshold voltage and forward body biasing techniques were applied to
further improve the performance of the adders. The PDP obtained using the forward body biasing technique shows an effective improvement compared to high threshold voltage and multi threshold voltage techniques. The forward biasing technique maintains a balance between delay reduction and increase in average power, thus reducing the power delay product when compared to the other two techniques.
AN ULTRA-LOW POWER ROBUST KOGGESTONE ADDER AT SUB-THRESHOLD VOLTAGES FOR IMPL...VLSICS Design
The growing demand for energy constrained applications and portable devices have created a dire need for
ultra-low power circuits. Implantable biomedical devices such as pacemakers need ultra-low power
circuits for a better battery life for uninterrupted biomedical data processing. Circuits operating in subthreshold
region minimize the energy per operation, thus providing a better platform for energy
constrained implantable biomedical devices. This paper presents 8, 16 and 32-bit ultra-low power robust
Kogge-Stone adders with improved performance. These adders operate at subthreshold supply voltages
which can be used for low power implantable bio-medical devices such as pacemakers. To improve the
performance of these adders in sub-threshold region, forward body bias technique and multi-threshold
transistors are used. The adders are designed using NCSU 45nm bulk CMOS process library and the
simulations were performed using HSPICE circuit simulator. Quantitative power-performance analysis is
performed at slow-slow (SS), typical-typical (TT) and fast-fast (FF) corners clocked at 50 KHz for
temperature ranging from 25̊C to 120̊C. For a supply voltage 0.3V, all the adders had the least PDP. Using
0.3V as the supply voltage, multi threshold voltage and forward body biasing techniques were applied to
further improve the performance of the adders. The PDP obtained using the forward body biasing
technique shows an effective improvement compared to high threshold voltage and multi threshold voltage
techniques. The forward biasing technique maintains a balance between delay reduction and increase in
average power, thus reducing the power delay product when compared to the other two techniques.
GENERIC SYSTEM VERILOG UNIVERSAL VERIFICATION METHODOLOGY BASED REUSABLE VERI...VLSICS Design
In this paper, we present Generic System Verilog Universal Verification Methodology based Reusable Verification Environment for efficient verification of Image Signal Processing IP’s/SoC’s. With the tight schedules on all projects it is important to have a strong verification methodology which contributes to First Silicon Success. Deploy methodologies which enforce full functional coverage and verification of corner cases through pseudo random test scenarios is required. Also, standardization of verification flow is needed. Previously, inside imaging group of ST, Specman (e)/Verilog based Verification Environment for IP/Subsystem level verification and C/C++/Verilog based Directed Verification Environment for SoC Level Verification was used for Functional Verification. Different Verification Environments were used at IP
level and SoC level. Different Verification/Validation Methodologies were used for SoC Verification across multiple sites. Verification teams were also looking for the ways how to catch bugs early in the design cycle? Thus, Generic System Verilog Universal Verification Methodology (UVM) based Reusable Verification Environment is required to avoid the problem of having so many methodologies and provides a standard unified solution which compiles on all tools.
Nexgen Technology Address:
Nexgen Technology
No :66,4th cross,Venkata nagar,
Near SBI ATM,
Puducherry.
Email Id: praveen@nexgenproject.com.
www.nexgenproject.com
Mobile: 9751442511,9791938249
Telephone: 0413-2211159.
NEXGEN TECHNOLOGY as an efficient Software Training Center located at Pondicherry with IT Training on IEEE Projects in Android,IEEE IT B.Tech Student Projects, Android Projects Training with Placements Pondicherry, IEEE projects in pondicherry, final IEEE Projects in Pondicherry , MCA, BTech, BCA Projects in Pondicherry, Bulk IEEE PROJECTS IN Pondicherry.So far we have reached almost all engineering colleges located in Pondicherry and around 90km
Efficient implementation of 2 bit magnitude comparator using ptIJARIIT
Nowadays the requirements of low power electronics play a vital role in various fields. In this paper we introducing
the novel comparator is one of the fundamental units in VLSI design and also it can be employed in various applications like
Digital Signal Processors (DSP) and Data Processing, Communication Systems, Medical Electronics etc., Comparator is
involved to the most basic arithmetic operation of compression between any two variables either it maybe an equal one or
unequal. In early days, the comparator techniques used to implement energy optimization in low power circuits but the static
power dissipation need to improve the comparator using logic styles. In this paper, the 2-bit comparator has been designed by
using pass transistor logic (PTL). PTL provide good performance by reducing transistor count as well as power because PTL
logic helps in reducing the transistor count compared to other logic operation. The design was implemented in Cadence
virtuoso TMSC 180nm CMOS technology and it’s obtaining the total power dissipation 1.394μw. PTL logic is used to reduce
both transistor count and power dissipation in magnitude comparator is used to improve the good quality performance of this circuit.
NEXGEN TECHNOLOGY as an efficient Software Training Center located at Pondicherry with IT Training on IEEE Projects in Android,IEEE IT B.Tech Student Projects, Android Projects Training with Placements Pondicherry, IEEE projects in pondicherry, final IEEE Projects in Pondicherry , MCA, BTech, BCA Projects in Pondicherry, Bulk IEEE PROJECTS IN Pondicherry.So far we have reached almost all engineering colleges located in Pondicherry and around 90km
Nexgen Technology Address:
Nexgen Technology
No :66,4th cross,Venkata nagar,
Near SBI ATM,
Puducherry.
Email Id: praveen@nexgenproject.com.
www.nexgenproject.com
Mobile: 9791938249
Telephone: 0413-2211159.
Java Web Application Project Titles 2023-2024.
🔗Email: jpinfotechprojects@gmail.com,
🌐Website: https://www.jpinfotech.org
📞MOBILE: (+91)9952649690.
Java Application Projects 2023 - 2024
Java Web Application Project Titles
E-Authentication System using QR Code and OTP
Student Attendance System Using QR-Code
Hall Ticket Generation System with Integrated QR Code
Certificate Authentication System using QR Code
QR Code-based Smart Vehicle Parking Management System
Employee Attendance System using QR Code
QR Code based Secure Online Voting System
QR Code Based Smart Online Student Attendance System
Cyber Security Projects
Detecting Malicious Facebook Applications
Detection of Bullying Messages in Social Media
Enhanced Secure Login System using Captcha as Graphical Passwords
Filtering Unwanted Messages in Online Social Networking User walls
Secure Online Transaction System with Cryptography
Detecting Mobile Malicious Webpages in Real Time
Credit Card Fraud Detection in Online Shopping System
Enhanced Data Security with Onion Encryption and Key Rotation
Detection of Offensive Messages in Social Media to Protect Online Safety
Healthcare Projects
Diabetes Prediction using Data Mining in Healthcare Management System
Online Hospital Management System
Online Oxygen Management System
Enhanced Hospital Admission System to Mitigate Crowding
Online Parking Booking System
E-Pass Management System | Curfew e-pass management system
Online Tender Management System
Online Toll Gate Management System
Online Election System
Panchayat Union Automation System
Smart City Project - A Complete City Guide Using Database
Visa Processing Management System
Cricket Win Predictor using Machine Learning
College Management System
Online college Counselling system
Online No Dues Management System
Online Student Mentoring System
Online Tuition Management System
Bike Store Management System
Computer Inventory System
Distilled Water Management System
Donation Tracking System | Online Charity Management System
Online Bug Tracking System
Online Content Based Image Retrieval System with Ranking Model
Online Crime File Management System
Online Courier Management System
Online Blood Bank Management System
Online Secure Organ Donation Management System
Connecting Social Media to E-Commerce
Twitter Based Tweet Summarization
Mental Disorders Detection via Online Social Media Mining
Detecting Stress Based on Social Interactions in Social Networks
Knowledge Sharing Based Online Social Network with Question and Answering System
Predicting Suicide Intuition in Online Social Network
Predicting Emotions of User in Online Social Network
Employee Payroll Management System
Human Resource Management System
Online Employee Tracking System
College Admission Predictor
Online Book Recommendation System
Personalized Movie Recommendation System
Product Recommendation System in Online Social Network
Mining Online Product Evaluation System based on Ratings and Review Comments
Online Book Buying and Selling
Implementation of pull up pull-down network for energy optimization in full a...IJARIIT
Nowadays the requirements of energy optimized low power circuits in higher-end applications such as
communication, IoT, biomedical systems etc., there are several techniques used to implement energy optimization in low power
circuits but the static power dissipation need to improve such kind of circuits. The conventional topology has been
implemented in basic logical gates but the delay and power much higher in each individual cell. Now we proposed an
unbalanced pull-up and pull-down network in full adder circuit using symbols. These techniques were employed to reduce the
static power dissipation and switching delay in each individual cell. The design was implemented in Cadence virtuoso TMSC
180nm CMOS technology and it’s obtaining the total power dissipation 5.128nW.The pull-up and pull-down network used to
reduce the static power dissipation in full adder is used to improve the operating speed of each individual.
Low Power Design of Standard Digital Gate Design Using Novel Sleep Transisto...IJMER
In the nanometer range design technologies static power consumption is very important
issue in present peripheral devices. In the CMOS based VLSI circuits technology is scaling towards
down in respect of size and achieving higher operating speeds. We have also considered these
parameters such that we can control the leakage power. As process model design are getting smaller
the density of device increases and threshold voltage as well as oxide thickness decrease to maintain
the device performance. In this article two novel circuit techniques for reduction leakage current in
NAND and NOR inverters using novel sleepy and sleepy property are investigated. We have proposed a
design model that has significant reduction in power dissipation during inactive (standby) mode of
operation compared to classical power gating methods for these circuit techniques. The proposed
circuit techniques are applied to NAND and NOR inverters and the results are compared with earlier
inverter leakage minimization techniques. All low leakage models of inverters are designed and
simulated in Tanner Tool environment using 65 nm CMOS Technology (1volt) technologies. Average
power, Leakage power, sleep transistor
Area efficient fixed-width squarer with dynamic error-compensation circuitLogicMindtech Nologies
VLSI Projects for M. Tech, VLSI Projects in Vijayanagar, VLSI Projects in Bangalore, M. Tech Projects in Vijayanagar, M. Tech Projects in Bangalore, VLSI IEEE projects in Bangalore, IEEE 2015 VLSI Projects, FPGA and Xilinx Projects, FPGA and Xilinx Projects in Bangalore, FPGA and Xilinx Projects in Vijayangar
A new method for self-organized dynamic delay loop associated pipeline with ...IJECEIAES
The minimization of propagation delay between pipeline stages is very important in wave propagation through pipeline-stages. The propagation delay can be minimized by minimizing the number of stages in a pipeline. In the proposed design a dynamic stage control is imparted in the pipeline. The propagation delay can be optimized in any type of pipeline by controlling number of stages dynamically. The pipeline interpretation helps a lot to overcome the flaws due to not ready sequence (NRS) and synchronization problems. It is observed that, in the pipeline design the basic and actively involved pipeline techniques are concerned with different challenges like clock, throughput, cell area, and sizes. As the data throughput increases the number of stages in pipeline also needs to be increased to meet the desired goal. In the case of unpredictable data speed, the definite number of pipeline stages creates severe problems. In this work a dynamic pipeline is integrated where the number of stages is dynamically changing depending up on data speed. In dynamic pipeline technique the circuit cell area of reconfigurable computing system (RCS) will be reduced dynamically at low-speed data transmission. In the high-speed data communication, the data speed is managed and controlled by dynamic delay loops.
In this paper a CMOS AND gate layout has been designed and simulated using 90nm technology. The layout has been designed using two approaches, namely fully automatic and semicustom. In fully automatic technique AND gate schematic is developed which is constructed into its equivalent spice file for the automatic layout generation. In semicustom technique layout has been developed mainly to optimize area and power. It can be observed from the simulated results that semicustom layout results in 11.2µm2 area consumption by consuming almost the same power as compared to fully automatic design.
Current Comparison Domino based CHSK Domino Logic Technique for Rapid Progres...IJECEIAES
The proposed domino logic is developed with the combination of Current Comparison Domino (CCD) logic and Conditional High Speed Keeper (CHSK) domino logic. In order to improve the performance metrics like power, delay and noise immunity, the redesign of CHSK is proposed with the CCD. The performance improvement is based on the parasitic capacitance, which reduces on the dynamic node for robust and rapid process of the circuit. The proposed domino logic is designed with keeper and without keeper to measure the performance metrics of the circuit. The outcomes of the proposed domino logic are better when compared to the existing domino logic circuits. The simulation of the proposed CHSK based on the CCD logic circuit is carried out in Cadence Virtuoso tool.
Nexgen Technology Address:
Nexgen Technology
No :66,4th cross,Venkata nagar,
Near SBI ATM,
Puducherry.
Email Id: praveen@nexgenproject.com.
www.nexgenproject.com
Mobile: 9751442511,9791938249
Telephone: 0413-2211159.
NEXGEN TECHNOLOGY as an efficient Software Training Center located at Pondicherry with IT Training on IEEE Projects in Android,IEEE IT B.Tech Student Projects, Android Projects Training with Placements Pondicherry, IEEE projects in pondicherry, final IEEE Projects in Pondicherry , MCA, BTech, BCA Projects in Pondicherry, Bulk IEEE PROJECTS IN Pondicherry.So far we have reached almost all engineering colleges located in Pondicherry and around 90km
Nexgen Technology Address:
Nexgen Technology
No :66,4th cross,Venkata nagar,
Near SBI ATM,
Puducherry.
Email Id: praveen@nexgenproject.com.
www.nexgenproject.com
Mobile: 9751442511,9791938249
Telephone: 0413-2211159.
NEXGEN TECHNOLOGY as an efficient Software Training Center located at Pondicherry with IT Training on IEEE Projects in Android,IEEE IT B.Tech Student Projects, Android Projects Training with Placements Pondicherry, IEEE projects in pondicherry, final IEEE Projects in Pondicherry , MCA, BTech, BCA Projects in Pondicherry, Bulk IEEE PROJECTS IN Pondicherry.So far we have reached almost all engineering colleges located in Pondicherry and around 90km
A verilog based simulation methodology for estimating statistical test for th...ijsrd.com
The low Power estimation is an important aspect in digital VLSI circuit design. The estimation includes a power dissipation of a circuit and hence this to be reduces. The power estimations are specific to a particular component of power. The process of optimization of circuits for low power, user should know the effects of design techniques on each component. There are different power dissipation methods for reduction in power component. In this paper, estimating the power like short circuit and the total power, power reduction technique and the application of different proposed technique has been presented here. Hence, it is necessary to provide the information about the effect on each of these components.
Extremely Low Power FIR Filter for a Smart Dust Sensor ModuleCSCJournals
Digital filters are common components in many applications today, also in for sensor systems, such as large-scale distributed smart dust sensors. For these applications the power consumption is very critical, it has to be extremely low. With the transistor technology scaling becoming more and more sensitive to e.g. gate leakage, it has become a necessity to find ways to minimize the flow of leakage in current CMOS logic. This paper studies sub-threshold source coupled logic (STSCL) in a 45-nm process. The STSCL can be used instead of traditional CMOS to meet the low power and energy consumption requirements. The STSCL style is in this paper used to design a digital filter, applicable for the audio interface of a smart dust sensor where the sample frequency will be 44.1 kHz. A finite-length impulse response (FIR) filter is used with transposed direct form structure and for the coefficient multiplication five-bit canonic signed digit [7] based serial/parallel multipliers were used. The power consumption is calculated along with the delay in order to present the power delay product (PDP) such that the performance of the sub-threshold logic can be compared with corresponding CMOS implementation. The simulated results shows a significant reduction in energy consumption (in terms of PDP) with the system running at a supply voltage as low as 0.2 V using STSCL.
An Ultra-Low Power Robust Koggestone Adder at Sub-Threshold Voltages for Impl...VLSICS Design
The growing demand for energy constrained applications and portable devices have created a dire need for ultra-low power circuits. Implantable biomedical devices such as pacemakers need ultra-low power circuits for a better battery life for uninterrupted biomedical data processing. Circuits operating in subthreshold region minimize the energy per operation, thus providing a better platform for energy constrained implantable biomedical devices. This paper presents 8, 16 and 32-bit ultra-low power robust Kogge-Stone adders with improved performance. These adders operate at subthreshold supply voltages which can be used for low power implantable bio-medical devices such as pacemakers. To improve the performance of these adders in sub-threshold region, forward body bias technique and multi-threshold transistors are used. The adders are designed using NCSU 45nm bulk CMOS process library and the simulations were performed using HSPICE circuit simulator. Quantitative power-performance analysis is performed at slow-slow (SS), typical-typical (TT) and fast-fast (FF) corners clocked at 50 KHz for temperature ranging from 25̊C to 120̊C. For a supply voltage 0.3V, all the adders had the least PDP. Using 0.3V as the supply voltage, multi threshold voltage and forward body biasing techniques were applied to
further improve the performance of the adders. The PDP obtained using the forward body biasing technique shows an effective improvement compared to high threshold voltage and multi threshold voltage techniques. The forward biasing technique maintains a balance between delay reduction and increase in average power, thus reducing the power delay product when compared to the other two techniques.
AN ULTRA-LOW POWER ROBUST KOGGESTONE ADDER AT SUB-THRESHOLD VOLTAGES FOR IMPL...VLSICS Design
The growing demand for energy constrained applications and portable devices have created a dire need for
ultra-low power circuits. Implantable biomedical devices such as pacemakers need ultra-low power
circuits for a better battery life for uninterrupted biomedical data processing. Circuits operating in subthreshold
region minimize the energy per operation, thus providing a better platform for energy
constrained implantable biomedical devices. This paper presents 8, 16 and 32-bit ultra-low power robust
Kogge-Stone adders with improved performance. These adders operate at subthreshold supply voltages
which can be used for low power implantable bio-medical devices such as pacemakers. To improve the
performance of these adders in sub-threshold region, forward body bias technique and multi-threshold
transistors are used. The adders are designed using NCSU 45nm bulk CMOS process library and the
simulations were performed using HSPICE circuit simulator. Quantitative power-performance analysis is
performed at slow-slow (SS), typical-typical (TT) and fast-fast (FF) corners clocked at 50 KHz for
temperature ranging from 25̊C to 120̊C. For a supply voltage 0.3V, all the adders had the least PDP. Using
0.3V as the supply voltage, multi threshold voltage and forward body biasing techniques were applied to
further improve the performance of the adders. The PDP obtained using the forward body biasing
technique shows an effective improvement compared to high threshold voltage and multi threshold voltage
techniques. The forward biasing technique maintains a balance between delay reduction and increase in
average power, thus reducing the power delay product when compared to the other two techniques.
GENERIC SYSTEM VERILOG UNIVERSAL VERIFICATION METHODOLOGY BASED REUSABLE VERI...VLSICS Design
In this paper, we present Generic System Verilog Universal Verification Methodology based Reusable Verification Environment for efficient verification of Image Signal Processing IP’s/SoC’s. With the tight schedules on all projects it is important to have a strong verification methodology which contributes to First Silicon Success. Deploy methodologies which enforce full functional coverage and verification of corner cases through pseudo random test scenarios is required. Also, standardization of verification flow is needed. Previously, inside imaging group of ST, Specman (e)/Verilog based Verification Environment for IP/Subsystem level verification and C/C++/Verilog based Directed Verification Environment for SoC Level Verification was used for Functional Verification. Different Verification Environments were used at IP
level and SoC level. Different Verification/Validation Methodologies were used for SoC Verification across multiple sites. Verification teams were also looking for the ways how to catch bugs early in the design cycle? Thus, Generic System Verilog Universal Verification Methodology (UVM) based Reusable Verification Environment is required to avoid the problem of having so many methodologies and provides a standard unified solution which compiles on all tools.
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Efficient implementation of 2 bit magnitude comparator using ptIJARIIT
Nowadays the requirements of low power electronics play a vital role in various fields. In this paper we introducing
the novel comparator is one of the fundamental units in VLSI design and also it can be employed in various applications like
Digital Signal Processors (DSP) and Data Processing, Communication Systems, Medical Electronics etc., Comparator is
involved to the most basic arithmetic operation of compression between any two variables either it maybe an equal one or
unequal. In early days, the comparator techniques used to implement energy optimization in low power circuits but the static
power dissipation need to improve the comparator using logic styles. In this paper, the 2-bit comparator has been designed by
using pass transistor logic (PTL). PTL provide good performance by reducing transistor count as well as power because PTL
logic helps in reducing the transistor count compared to other logic operation. The design was implemented in Cadence
virtuoso TMSC 180nm CMOS technology and it’s obtaining the total power dissipation 1.394μw. PTL logic is used to reduce
both transistor count and power dissipation in magnitude comparator is used to improve the good quality performance of this circuit.
NEXGEN TECHNOLOGY as an efficient Software Training Center located at Pondicherry with IT Training on IEEE Projects in Android,IEEE IT B.Tech Student Projects, Android Projects Training with Placements Pondicherry, IEEE projects in pondicherry, final IEEE Projects in Pondicherry , MCA, BTech, BCA Projects in Pondicherry, Bulk IEEE PROJECTS IN Pondicherry.So far we have reached almost all engineering colleges located in Pondicherry and around 90km
Nexgen Technology Address:
Nexgen Technology
No :66,4th cross,Venkata nagar,
Near SBI ATM,
Puducherry.
Email Id: praveen@nexgenproject.com.
www.nexgenproject.com
Mobile: 9791938249
Telephone: 0413-2211159.
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Delay Analysis for Current Mode Threshold Logic Gate Designs
1. Delay Analysis for Current Mode Threshold Logic Gate
Designs
ABSTRACT:
Current mode is a popular CMOS-based implementation of threshold logic
functions, where the gate delay depends on the sensor size. This paper presents a
new implementation of current mode threshold functions for improved gate delay
and switching energy. An analytical method is also proposed in order to identify
quickly the sensor size that minimizes the gate delay. Simulation results on
different gates implemented using the optimum sensor size indicates that the
proposed current mode implementation method outperforms consistently the
existing implementations in delay as well as switching energy. The proposed
architecture of this paper analysis the logic size, area and power consumption using
Tanner tool.
SOFTWARE IMPLEMENTATION:
Tanner tool