The document describes a parallel single-rail self-timed adder designed using a recursive approach for multibit binary addition. It highlights the adder's ability to achieve logarithmic performance without special speedup circuitry while providing a practical implementation with a completion detection unit. The design utilizes industry-standard simulation tools and has no significant limitations regarding high fanouts, requiring a high fan-in gate managed by parallel transistor connections.

1. Logic Mind Technologies
Vijayangar (Near Maruthi Medicals), Bangalore-40
Ph: 8123668124 // 8123668066
ecursive Approach to the Design of a Parallel
Self-Timed Adder
Abstract—This brief presents a parallel single-rail self-timed adder. It is based on a
recursive formulation for performing multibit binary addition. The operation is
parallel for those bits that do not need any carry chain propagation. Thus, the
design attains logarithmic performance over random operand conditions without
any special speedup circuitry or look-ahead schema. A practical implementation is
provided along with a completion detection unit. The implementation is regular
and does not have any practical limitations of high fanouts. A high fan-in gate is
required though but this is unavoidable for asynchronous logic and is managed by
connecting the transistors in parallel. Simulations have been performed using an
industry standard toolkit that verify the practicality and superiority of the proposed
approach over existing asynchronous adders.
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2. SOFTWARE REQUIREMENT:
 ModelSim6.4c.
 Xilinx 9.1/13.2.
HARDWARE REQUIREMENT:
 FPGA Spartan 3.
PROJECT FLOW:
First Review:
Literature Survey
Paper Explanation
Design of Project
Project Enhancement explanation
Second Review:
Implementing 40% of Base Paper
Third Review
Implementing Remaining 60% of Base Paper with Future Enhancement (Modification)
For More Details please contact
Logic Mind Technologies
Vijayangar (NearMaruthi Medicals), Bangalore-40
Ph: 8123668124 // 8123668066
Mail: logicmindtech@gmail.com