This document discusses various concepts in data flow modeling and VHDL, including: - Using <= to assign signals and define data flow - Concurrent and process modeling - Conditional signal assignment using when/else and with/select statements - The unaffected value for conditional assignments It also provides examples of modeling common logic functions like muxes, decoders, and tri-state buffers in VHDL using these concepts.

1. Data flow modelling

2. Modeling the Dataflow way
• Uses statements that defines the actual flow of
data.....
such as,
x <= y -- this is NOT less than equal
This assigns the boolean signal x to the value of
boolean signal y... i.e. x = y
this will occur whenever y changes....

3. Concurrent Statements
● Concurrent statements are executed at the same time,
independent of the order in which they appear
architecture……
Begin
A<=B;
Z<=A;
End;

4. Process model(in behavioral modeling)
for this
Architecture..
Begin
process (B)
A<=B;
Z<=A;
end process;
end;

5. Three inverting buffers
entity INV is
port (A:in bit; Z:out bit);
end INV;
architecture DELAY of INV is
signal B,C : bit;
begin
Z <= not C;
C <= not B;
B <= not A;
end DELAY;

7. Conditional Signal Assignment –
When - Else
● Condition is a boolean expression
● Mandatory else path, unless unconditional assignment
● conditions may overlap
● Equivalent of if ..., elsif ..., else constructs

8. TARGET <= VALUE;
TARGET <= VALUE_1 when CONDITION_1 else
VALUE_2 when CONDITION_2 else
. . .
VALUE_n;
● Note that the condition clauses must evaluate to a
logical expression.

9. entity CONDITIONAL_ASSIGNMENT is
port (A, B, C, X : in bit_vector (3 downto 0);
Z_CONC : out bit_vector (3 downto 0);
Z_SEQ : out bit_vector (3 downto 0));
end CONDITIONAL_ASSIGNMENT;
architecture EXAMPLE of CONDITIONAL_ASSIGNMENT is
begin
-- Concurrent version of conditional signal assignment
Z_CONC <= B when X = "1111" else
C when X > "1000" else
A;

10. -- Equivalent sequential statements
process (A, B, C, X)
begin
if (X = "1111") then
Z_SEQ <= B;
elsif (X > "1000") then
Z_SEQ <= C;
else
Z_SEQ <= A;
end if;
end process;
end EXAMPLE;

11. 4 to 1 Mux (Conditional Concurrent
Form)
Z <= A when s = “00” else
B when s = “01” else
C when s = “10” else
D;
• In the last case, we did not specify a condition; this
is the “when no other condition is met” case.
• Note also that we can conditionalize the last case by
if so, we must ensure that all possible condition
combinations are addressed.

12. Selected Signal Assignment –
with - select
with EXPRESSION select
TARGET <= VALUE_1 when CHOICE_1,
VALUE_2 when CHOICE_2 | CHOICE_3,
VALUE_3 when CHOICE_4 to CHOICE_5,
· · ·
VALUE_n when others

13. ● The “choices” are values of the discriminator; either.
– single value: when “0001”,
– multiple values: when “0100” | “0110” | “1000”,
– value range: when“1010” to “1111”,
– everything else: when others;
● The last case “when others” must be the last clause if used
● Comma separates clauses, semicolon ends the statement

14. entity SELECTED_ASSIGNMENT is
port (A, B, C, X : in integer range 0 to 15;
Z_CONC : out integer range 0 to 15;
Z_SEQ : out integer range 0 to 15);
end SELECTED_ASSIGNMENT;
architecture EXAMPLE of SELECTED_ASSIGNMENT is
begin
-- Concurrent version of selected signal assignment
with X select
Z_CONC <= A when 0,
B when 7 | 9,
C when 1 to 5,
0 when others;

15. -- Equivalent sequential statements
process (A, B, C, X)
begin
case X is
when 0 => Z_SEQ <= A;
when 7 | 9 => Z_SEQ <= B;
when 1 to 5 => Z_SEQ <= C;
when others => Z_SEQ <= 0;
end process;
end EXAMPLE;

16. The UNAFFECTED value
MARK_FLAG <= BKDET after 5 ns when STORBE = „0‟ else
unaffected;
● unaffected is equivalent to null statement
Process
Begin
if STROBE = „0‟ then
MARK_DET <= BKDET after 5 ns;
else null;
end if;
wait on STROBE, BKDET;
end process

17. Exercise Questions
● 1. 3-to-8 decoder with enable input and active-high
output (Using concurrent signal assignment
statements).
● 2. 3-to-8 decoder with enable input and active high
output (Using With…..select….)
● 3. Three –input majority function.
● 4. Three –input minority function.
● 5. Tri-state buffer with propagation delay of 10ns
(try using when….else statement)
● 6. Three-input ex-nor gate

18. References
● [1]. “Digital Systems Design Using VHDL” by
Charles H Roth, Jr., Thomson Learining,
Brooks/Cole.
● [2]. “VHDL Primer” by J Bhasker, PHI, Third
edition.