Shubham Kumar Dokania completed his M.Tech in VLSI Design from IIT Dhanbad in 2021, with a CGPA of 9.2. For his final year project, he developed BIST for a DSP core in an FPGA SOC using Verilog to decrease comparator requirements and increase fault coverage. He has experience with projects involving security alarms, solar panel tracking systems, and Bluetooth-based home automation using Arduino. His skills include Verilog, CMOS amplifiers, VHDL, and Vivado. He holds achievements such as a GATE score of 745 and being in the top 3 of his M.Tech program so far.