The document describes an ISA design project for a computer architecture course. It outlines the requirements for the project, which include having the same number of instructions, a minimum number of registers of flexible length, 1kb of main memory, and 9 instruction types. It then proposes a RISC-style instruction set with 3 formats (R, I, C) and defines 9 instructions - ADD, SUB, immediate ADD, immediate SUB, TRUE, FALSE, JUMP, LOAD, STORE. The number of registers is proposed to be 32 to match RISC-V and the length of registers is to be flexible.

1. ISA DESIGN PROJECT
COMPUTER
ARCHITECTURE
신현준

2. 요구사항
1. 명령어의 갯수가 같아야 한다.
2. 레지스터 갯수 및 길이는 자유(최소한의 갯수와 길이)
3. 메인메모리 1kb
4. 수행하는 명령어 종류 총 9개( + , - , immediate +,-, ==, !=, jump, load, store)
5. 명령어 type, field, name 자유

3. 레지스터 갯수와 길이
32개와 32bits ?

4. Instruction Set (R, I, C)
OP
4 bits
Function Code S1 S2 D
R-type
I-type
OP
4 bits
S1 D
Constant or address
Logical
J-type
OP Constant or address
4 bits
MIP를 기반으로 이름, 순서 변경

5. ADD와 SUB
OP Function Code S1 S2 D
Logical
R-type
0000 0 ADD
1 SUB
OP S1 D
Constant or address
I-type
0001
수행해야할 명령어가 적기 때문에, Function Code가 있을 필요가 없다.

6. Instruction Set (R, I, C)
OP
4 bits
S1 S2 D
R-type
I-type
OP
4 bits
S1 D
Constant or address
J-type
OP Constant or address
4 bits
OP: Operation Code
S1: First source register
S2: Second source register
D: Destination register
5 bits 5 bits 6 bits
5 bits 6 bits
5 bits
16 bits

7. ADD와 SUB, Immediate Add, Sub
OP S1 S2 D
R-type
I-type
OP S1 D
Constant or address
0000. add
0001. sub
0010. addi
0011. subi

8. True and False
I-type
OP S1 D
Constant or address
0100. true
0101. false

9. When something happened and then
(Unconditional Jump)
J-type
OP Constant or address
0110. Jump

10. Load와 Store
I-type
OP S1 D
Constant or address
0111. load
1000. store

11. Summary
0000. add
0001. sub
0010. addi
0011. subi
0100. true
0101. false
0110. Jump
0111. load
1000. store
ISA The number of Registers The length of Registers
20 bits
?

12. Why RISC-V architecture has 32 registers?
https://www.vlsisystemdesign.com/why-risc-v-architecture-has-32-registers/
All registeres in a RISC-V architecture is represented by 5 bit binary pattern
5 bits to represent registers, which means total number of register is 2^5 = 32
registers
Risc-v는 워드 단위로 일을 처리
“Simplicity favors regularity and good design demands good compromises”
나도 레지스터의 할당 단위를 5bit로 고정했으니, 나도 32개가 필요하구나.

13. The number of Registers
Name Number Use
$zero $0 Constant 0 for speed up the putting into var or let
$at $1 Assembler temporary for machine instructions that
pseudoinstructions are translated into.(e.g.,load)
$v0 - $v1 $2 - $3 values for function returns and expression evaluation
$a0 - $a3 $4 - $7 function arguments
$t0 - $t9 $8 - $15, $24 - $25 Temporary Registers
$s0 - $s7 $16 - $23 Saved Registers
$k0 - $k1 $26 - $27 Kernel Registers
gp $28 Global Data Pointer
sp $29 Stack Pointer
fp $30 Frame Pointer
ra $31 Return Address

14. Summary
0000. add
0001. sub
0010. addi
0011. subi
0100. true
0101. false
0110. Jump
0111. load
1000. store
ISA The number of Registers The length of Registers
20 bits
32ea

15. Thank you!