1. 3D Stacked Architectures
with Interlayer Cooling -
CMOSAIC
Prof. John R. Thome, LTCM-EPFL, Project
Coordinator
Prof. Yusuf Leblebici, LSM-EPFL
Prof. Dimos Poulikakos, LTNT-ETHZ
Prof. Wendelin Stark, FML-ETHZ
Prof. David Atienza Alonso, ESL-EPFL
Dr. Bruno Michel, IBM Zürich Research
Laboratory

2. CNN: Computing Electrical Power Consumption

3. Two-Phase Cooling of 3D
Stacked Microprocessors
PhD student: Yassir
3D integration & thermal management
Madhour
Vertical electrical interconnect:
Through-Silicon-Via (TSV)
3D integration opportunities & threats How to remove heat from a chip stack: interlayer
cooling
 Global wire length reduction
 Memory-on-core stacking with vertical electrical  Scales with number of dies whereas backside
communication → massive core-to-cache bandwidth cooling scales only with die area
 Shorter wires & no repeaters → improved power 3  Heat removal: refrigerant two-phase cooling
4
efficiency  Two-phase: no electrical insulation, minimal
 Threats: heat flux accumulation, additional thermal temperature gradients, automatic hot-spot heat
resistances, peak temperatures removal BUT dry-out problem, complex system
IBM: Thomas Brunschwiler, Ute Drechsler and Martin Witzig

4. Test
Vehicles for Stacked
Microprocessors PhD
• Interlayer cooling with evaporated dielectric fluid.
• Solder: « eutectic » 3.5Ag-Sn, low melting temperature: 221°C. student:
• Designs A & B Yassir
• Present project status: package design optimization.
Madhour
A
B
IBM:
Thomas
Brunschwiler
, Ute C4 solder bumps as «pin fins»
Diameter: 50 to 100μm
Drechsler Pitch: 100 to 200μm
Heat transfer: microchannels / pin fins
Thin film bond: 5 to 10μm
and Martin

5. Wafer-Level TSV Compatible to
Liquid Cooling of High Performance CMOS
Ph.D. Students: Michael Zervas, Yuksel Temiz
• Wafer-level and CMOS compatible TSV process. Daisy-chain interconnections patterned
on TSVs.
• Very flat surface after TSV fabrication that allows.
further lithographic steps.
• 900 TSVs connected in a single daisy chain.
• Resistance per TSV 0.7 Ohm.

6. Die-Level Through-Silicon-Via Fabrication
Platform
Ph.D. Students: Yuksel Temiz, Michael Zervas
• Wafer reconstitution and stencil lithography.
Stencil Lithography
• Die-level etching and thin-film patterning.
• Die-level Cu electroplating.
Electroplating

7. Fabrication of Two-Phase Cooling Test
Chips
Ph.D. Students: Yuksel Temiz (LSM), Sylwia Szczukiewicz (LTCM)
• Front-side metal patterning.
• Front-side DRIE for inlet/outlet
openings.
• Back-side DRIE for microchannels.
• Silicon-Pyrex Anodic Bonding
Back-side
Front-side

8. 2D Multi-Microchannel Flow Boiling
Experiment
Ph.D.: Sylwia Szczukiewicz – Achievements to date
CCD camera
DAQ system
M icro-evaporator
I R camera
Exploded view of the LTCM flow boiling test facility
• A novel in-situ ‘pixel by pixel’ technique has been4 developed to
experimental setup
calibrate the raw infra-red images from IR camera running at 60fps.
• So far, 752’640 local temperature measurements for one multi-
microchannel evaporator with 100x100 micron channels have been
recorded.

9. 2D Multi-Microchannel Flow Boiling Experiment
Ph.D.: Sylwia Szczukiewicz – 2D visualisation of two-phase
refrigerant flow
Multi-microchannel evaporator having 67 channels with the inlet orifices e=2 and 100x100μm
cross-section areas, Tsat=31.96oC, ΔTsub=5.63K, q=30.69W/cm2
G=496.1kg/m2,s,
slow motion (30fps),
CCD recorded
@2000fps,
IR recorded @60fps
For the test section having the
orifices with the expansion ratio
Flow direction e=2, the flow tends to stabilize at
the relatively high mass fluxes
and heat fluxes.
G=1643.02kg/m2s,
slow motion (30fps),
CCD recorded @2000fps,
IR recorded @60fps

10. 3D ALE-FEM for Microscale Two-Phase
Flows
Ph.D.: Gustavo Rabello dos standard approach Lagrangian approach
Anjos surf
ace
surf
a ce
Development:
[1] Comparison of surface [1]
representations;
[2] Arbitrary Lagrangian-Eulerian
Technique;
[3] Test case: 2D microchannel and [2] mesh velocity gravity surface
tension
3D rising bubble. Lagrangian
[4] 3D bubble motion - video
Goals: Eulerian
• Develop a 3D Arbitrary [3] 2D microchannel
Lagrangian-Eulerian Finite velocity
Element code;
• Coupled heat transfer and two-
phase flow 3D rising bubble
3
• Predict flows in microscale
gravity
complex geometries;
• Design tool for micro evaporators.
simulation time

11. 3D ALE-FEM for Microscale Two Phase
Flows
Ph.D.: Gustavo Rabello dos
Anjos
3D rising bubble:
type: low velocity
view: bubble rising,
insertion, flipping
and deletion of top
grid points
insertion: top view
deletion: bottom
view
side bottom

12. 3D ALE-FEM for Microscale Two Phase
Flows
Ph.D.: Gustavo Rabello dos
Anjos
3D rising bubble:
type: high velocity
view: bubble rising,
insertion, flipping
and deletion of top
grid points
insertion: top view
deletion: bottom
view
side bottom

13. Investigation of Integrated Water Cooling of 3D integrated Electronics
An experimental study: PhD student Adrian Renfer
Single cavity of a Increased pressure drop at Instantaneous -Particle Image
3D chip stack high flow rates Velocimetry
Vortex shedding induced flow impingement on
Fluctuations are amplified towards the outlet micropin fins
 Higher pumping power
Benefits of enhanced mixing
 High heat transfer
 Non-uniform micropin fin density for
systematic hot spot cooling
inlet center outlet Planned: measure and evaluate
 Heat transfer
Flow direction
 Vortex shedding frequency
Publication: Renfer et al., Experiments in Fluids (2011)  Global flow visualization

14. Performance Evaluation of Cooling Structures for 3D Chip Stacks
A computational study: PhD student Fabio Alfieri
Pin-Fins Inline (PFI) Microchannels (MC) Parallel Plates (PP)
Goals:
Q Q Q
•Evaluate performance of cooling structures
P
•Provide design guidelines for 3D chip stacks P
H
D H H
Experimental validation Pressure drop and heat transfer coefficients
Transition
Parallel plates
I) II) Pin-Fins
Microchannels
Currently underway:
Transitional regime: vortex shedding
- Impact on the performance of:
 pin-fins density adjustment Boundary layer
 non-homogeneous heat fluxes regeneration
x
Nu  ARe Pr  x L

- Modeling of entrance region:
Publications: - Alfieri et al., 3D Integrated Water Cooling of a Composite Multilayer Stack of Chips, J. Heat Transfer, 2010
- Alfieri et al., Performance Evaluation of Cooling Structures for 3D chip stacks (to be submitted)

15. Superhydrophobic Surfaces
Ph.D. Student: Michael Rossier
Goals
Production of a highly hydrophobic
surface to reduce the pressure drop in
microchannel with application for
water cooling systems
Approach
(1) Creation of a nanostructure (silicon
etching)
(2) Surface functionalization of the Needle-like silicon etching
created structure (fluorosiloxane)
3 4
“Needle-like” silicon structures: non-functionalized (left); functionalized with perfluorooctyltriethoxysilane (right)

16. 3D ICE: a new thermal simulator for 3D ICs with
interlayer
liquid cooling– Arvind Sridhar, EPFL-ESL
• FIRST-EVER compact modeling based thermal simulator for ICs with microchannel liquid
cooling
• Available as an open source Software Thermal Library at http://esl.epfl.ch/3D-ICE
• More than 35 (and counting!) research groups world-wide are using 3D-ICE
3D-ICE 1.0
• based on compact transient thermal modeling Rconv
(CTTM)
• 975x Faster! than commercial CFD tools
even for small problems
Coolant Flow 3D-ICE 2.0
Rcond Rconv • Advanced model for Enhanced Heat Transfer
Geometries (e.g., Pin Fins)
• 40x Faster! than conventional CTTM
{ X3D-ICE(tn+1) }
3D-ICE optimized as Neural Network based simulator for massively
parallel Graphics Processing Units (GPUs)
• It learns from 3D-ICE test simulations Training
Algorithm
• then works as stand-alone simulator { X(tn) }
• 100x Faster! than conventional 3D-ICE model { U(tn+1) } Neural Network
For more information on 3D-ICE please visit the poster -based simulator { XNN(tn+1) }
Future Work:
•To model entrance-region effects in microchannels
•Incorporate two-phase flows

17. Thermal Modeling and Active Cooling
Management for 3D MPSoCs – Mohamed M.
Sabry, EPFL-ESL
•Goals
Achieve thermal balance in 3D MPSoC tiers
No thermal runaway situations (thermal violations)
Minimal performance degradation
Minimal energy consumption Scheduler Power Manager (DPM)
Flow-rate actuator
•Proposed technique
Design-time run-time management strategy
•Design-time Control knobs identification
Electronic-based:
Dynamic Voltage and Frequency Scaling
Mechanical-based:
Transient Temperature
Dynamic Varying Flow rate Response
for Each Unit
•Run-time thermal management
Fuzzy-logic control
Rule-base look-up table control
Low complexity
Low computation overhead
•Achievements
Thermal violations 0%
Performance degradation 0.01%
Energy reduction up to 35%

18. MicroCool: Nano-Tera ED Training for 3D-
IC’s
PI: Prof. J.R. Thome

19. 3D-IC Cooling: Public Announcement by
IBM CEO

20. CMOSAIC: Technological Aims
 CMOSAIC aims to make an important
contribution to the development of the
first 3D computer chip with a
functionality per unit volume that
nearly parallels the functional density
of a human brain.
 A 3D computer chip with integrated
cooling system is expected to:
-Overcome the limits of air cooling
-Compress ~1012 nanometer sized functional
units 1000000
(1 Tera) into one cubic centimeter 100000
Wire Count
10000
Yield 10-100 fold higher connectivity 1000
-Cut energy and CO2
100
emissions drastically 0 2 4
Wire Length (mm)
6 8