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οƒ˜ Advancements in Lithography
οƒ˜ Evolution of Packaging
οƒ˜ Advanced Packaging
οƒ˜ TSV trends
οƒ˜ Monolithic 3DI Manufacturing
οƒ˜ 3D integration with TSV – challenges
οƒ˜ Existing metrology tools – discussion on a few
οƒ˜ Holographic technique - proposal
οƒ˜ Opportunities for 3D integration with optical
interconnects
οƒ˜ Metrology for optical interconnects
Photolithography: Small mask feature (d)-> Large Lens
οƒ˜ Multiple lithography steps
οƒ˜ Pitch halving-quartering etc.
-> costly
οƒ˜ 2D moving ahead to
1x nm scales.
οƒ˜ Waiting for High
Power EUV
οƒ˜ Vertical dimension making up
Lack of 2D scaling
Source: Sam Shivashankar, YouTube- nanolearning
Rayleigh Criteria-> π‘˜1 can’t go below 0.3 !
-> use small πœ†, πΏπ‘Žπ‘Ÿπ‘”π‘’π‘Ÿ 𝑁𝐴 -> hitting limits
Moving forward
Source: Mentor
Hybrid Memory Cube - Micron
Pierre Lartigues Field , 3D Plus USA
Flash Memory Summit 2012 Santa Clara, CA -
Current common packaging
Developing, TSV approach:
More interconnects and shorter
Interconnects -> Higher bit rate
Disadvantages of thinner longer wire interconnect:
1. Insufficient bandwidth, slow rise/fall pulse
2. Skin effect, Dielectric loss
3. Cross-talk
4. Low Bit-rate (B) between memory and CPU β†’ Memory wall
Bit-rate 𝐡 𝛼 𝐴/𝑙2
David Miller, Opt. Inter., 1997, Proc IEEE June 2000
Currently CPUs are faster but memory to CPU Bit-transfer rate is
slow. We want higher performance…
Source: Yole
In monolithic approach active layers and devices on them are built
sequentially in bottom up approach on top of a wafer.
Pros: The vertical interconnects are formed between layers rather than
chips, using vias in the π‘›π‘š rather than πœ‡π‘š range.
Cons: High quality active layer isolation need to be formed between each
active layers.
2. Crystallinity of upper layers is often imperfect.
3. This approach works only if polycrystalline silicon could be used for
making devices.
Reference: 3D Integration for VLSI Systems
Chuan Seng Tan, Kuan-Neng Chen, Steven J. Koester
οƒ˜ Better way : Stack chips with devices
1. Temporary bonding needed before forming via, for thinning by CMP and debonding and
bonding again is a very complex and delicate process.
2. Thermal management issue:
β€’ Stacking of memory chips alone does not produce heat issues, but integration with logic
Chip will have issues as neighboring memory chip will get high heat from adjacent
Logic chip.
β€’ Copper via might help themselves will conduct out some heat but may not be enough.
β€’ Low cost thermally aware via design is necessary
3. Copper reacts with Si, so passivation layer must be formed in the via walls before
filling in via with Cu, which is challenging
4. Stress is another issue:
Thermal expansively: Cu - 16.7ppm/C
W – 6-8 ppm/C
Si – 2.6 ppm/C
-> Stress development on wafer when TSVs expands.
β€’ Thinned wafer/die handling and bow
management
β€’ Si wafer cracking
β€’ Supply of micro-bump between stacks.
β€’ Defect visibility, measurement sensitivity and
identification
β€’ Complexity of the system, hidden structures
β€’ Design Test etc.
οƒ˜ Reliable non-destructive
metrology is needed
οƒ˜ Excellent tool for distinguishing and
quantifying crystallinity of silicon
surface
οƒ˜ Crystalline silicon
has very sharp peaks, such as the
one centered at ~ 520 cm-1
οƒ˜ Also, Micro-Raman spectroscopy:
useful to detect local stress on surface
Thesis: Keshab Raj Paudel, University of Missouri
𝑋𝑃𝑆, π‘ˆπ‘ƒπ‘†: 𝐸 𝐡 = β„Žπœˆ βˆ’ 𝐸 𝐾 βˆ’ π‘Š
𝐴𝐸𝑆: 𝐾. 𝐸. = (𝐸 πΎβˆ’πΈπΏ1) βˆ’ 𝐸23
Wide scan of 10nm Au nanoparticle on
Silicon surface
Angle resolved method:
-> Sensitive to nm scale layers
οƒ˜ Chemical analysis of surface
οƒ˜ Quantitative analysis
Dissertation: Keshab Raj Paudel, University of Missouri
οƒ˜ Very sensitive and fast compared to
dispersive IR absorption technique.
οƒ˜ Great for surface chemical analysis.
οƒ˜ Observation of Si-O bands are very intense.
C-H, C-C etc. modes characterize/identify
materials on Silicon wafer
Natural Diamond
Source: OLYMPUS
3D Metrology using IR Microscopy
A non-destructive imaging technique
β€’ In-line monitoring of the 3D bonding process:
β€’ Overlay alignment offset monitoring
β€’ Tracking process variations
β€’ Post bond defect inspection and review
οƒ˜ Confocal NIR microscopy using
interferometry looks further
Promising and is among already available
technologies and offers has new
possibilities
Limit: Can see only up to πŸ–πŸŽπŸŽ ππ’Ž inside
David Bernard, John Tingay et. al. "THE X-RAY METROLOGY OF TSVS AND
WAFER BUMPS” - Nordson DAGE, Feb 3, 2015
Oblique view x-ray image of 10 x 100 ΞΌm TSVs.
The lighter areas within the TSVs are voids.
X-ray image of 50 ΞΌm
diameter wafer bumps.
Top-down image.
Computer Tomography
Can limit X-ray beam from
0.1πœ‡π‘š π‘‘π‘œ 100πœ‡π‘š for higher resolution X βˆ’ ray imaging
Working: Total External Reflection,
Critical incident angle,
πœƒπ‘ π‘Ÿπ‘Žπ‘‘π‘–π‘Žπ‘› = 002 βˆ— 𝜌 (
𝑔
π‘π‘š3)/𝐸(π‘˜π‘’π‘‰)
Ref.: X-Ray Spectrometry: Recent Technological Advances
edited by Kouichi Tsuji, Jasna Injuk, RenΓ© Van Grieken
οƒ˜ Higher resolution than standard techniques
οƒ˜ Ultrasonic transducer to scan the wafer for defects that
modify the reflection of sound waves.
οƒ˜ Excels at finding voids and cracks,
Cons: Wafer needs to be immersed in a sound-conducting
liquid, usually distilled water.
οƒ˜ This requires a cleaning step after the sonic scan is
generated, while limiting application to wafers which will
not be contaminated by immersion.
οƒ˜ Relatively coarse with lateral resolution.
SEMICONDUCTOR International , August 2009
Acoustic image of a crack at
the bond interface in an Au-Si
bonded wafer pair.
Phase difference:
Ξ“ =
2πœ‹ 𝑛1 π‘₯1 βˆ’ 𝑛2 π‘₯2
πœ†
Light source
To spectrometer
οƒ˜ Non-destructive method
οƒ˜ Based on spectral reflectometry
οƒ˜ Several theoretical models (common: Rigorous Coupled Wave Theory)
οƒ˜ Highly promising
Source: IBM, ECTC 2014
Top CD and Depth
High Precision Allows Effective Control of Etch Rate and Uniformity
Source: IBM, ECTC 2014
Marvin B. Klein, W.E. Moerner et al., Optics Communications 162, 1999. 79–84
O. Ostroverkhova, W.E. Moerner et al., Chemical Reviews, Vol. 104, No. 7, 3267-3314, 2004
Schematic diagram of a laser ultrasonic receiver based on two-wave mixing
PR material: PVK:7-DCST:BBP:C60
οƒ˜ Major Advantage: Insensitive to fluctuations in the frequency of the laser
οƒ˜ Minimum detectable displacement: πœΉπ’π’Šπ’Ž
π’Šπ’…π’†π’‚π’
= 𝟐. πŸ• Γ— πŸπŸŽβˆ’πŸ–
π’π’Ž
οƒ˜ Varieties of PR materials developed thus far.
οƒ˜ Inexpensive experimental set up for R&D
οƒ˜ Dynamic hologram
οƒ˜ Strong ties with related people
Light: Science & Applications (2012) 1, e36; doi:10.1038/lsa.2012.36
www.nature.com/lsa
Driving factors:
οƒ˜ High density, multi-wavelength low-power photonics connectors ->
Enabler for Tbps applications
οƒ˜ High density photonics in 3DI-> Extreme 3D
Source: Emerging Technologies and Market Trends of Silicon
Photonics – S.BernabΓ© ECTC 2014
Knots and bolts for optical interconnects
1. Lasers
2. Waveguides – Si, cladded with SiO2
3. Ring resonators
4. Diode detectors (MSM, PIN III-V detectors)
5. Optical amplifiers ( e.g.. Erbium booster)
Challenges: Metrology again
1. Laser mode validation using external mode analysis tools such as scanning FB
Interferometer (which are commercially available, I have experience on such tools)
2. Pulse analysis using high speed spectrum analyzers ( e.t. Tektronix spectrum analyzer)
Check for stretch effect and intensity loss. Bit Error Rate (BER).
3. Test against micro bends and loss. – Challenging when waveguides are in the bulk of 3D
Geometry (good thing is that Si is transparent to IR), easier only in 2D geometry
Scanning Fabry-Perot Interferometer
Measures Laser linewidth as well.
Advanced Optics Lab, University of Missouri , Columbia
Tool not shown
resonance condition πœ† =
2𝑑
π‘š
οƒ˜ Speed becomes infinite in ENZ media.
Or
οƒ˜ Waves inside ENZ materials have very long
wavelength and essentially
have a uniform phase throughout the
propagation distance.
οƒ˜ Connect the two waveguides by an ENZ material, the coupling is better if the channel
is narrower !
οƒ˜ Metal clad waveguides near their cutoff frequency can mimic the ENZ material in the sense
that the effective mode index can approach zero.
Science, Vol. 340 no. 6130 pp. 286-287, 2013
𝚫 Γ— 𝑬 = π’ŠπŽππ‘―
𝚫 Γ— 𝑯 = 𝟎
𝚫 𝟐
𝑬 =
𝟏
𝒄 𝟐 (𝝏 𝟐
𝑬/𝝏𝒕 𝟐
)
οƒ˜ 3DI manufacturing: rapidly developing and
promising with TSV
οƒ˜ Existing metrology tools: not sufficient for TSV
technology
οƒ˜ Optical scatterometry: several variants/models,
need further development
οƒ˜ Interferometric technique with PR materials:
Promising opportunity for metrology development
οƒ˜ Hybrid photonic integration: Progressing and it is
the future of high speed integration -> careful
optical studies/tests needed
3 di metrology-slideshare

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3 di metrology-slideshare

  • 1.
  • 2. οƒ˜ Advancements in Lithography οƒ˜ Evolution of Packaging οƒ˜ Advanced Packaging οƒ˜ TSV trends οƒ˜ Monolithic 3DI Manufacturing οƒ˜ 3D integration with TSV – challenges οƒ˜ Existing metrology tools – discussion on a few οƒ˜ Holographic technique - proposal οƒ˜ Opportunities for 3D integration with optical interconnects οƒ˜ Metrology for optical interconnects
  • 3. Photolithography: Small mask feature (d)-> Large Lens οƒ˜ Multiple lithography steps οƒ˜ Pitch halving-quartering etc. -> costly οƒ˜ 2D moving ahead to 1x nm scales. οƒ˜ Waiting for High Power EUV οƒ˜ Vertical dimension making up Lack of 2D scaling Source: Sam Shivashankar, YouTube- nanolearning Rayleigh Criteria-> π‘˜1 can’t go below 0.3 ! -> use small πœ†, πΏπ‘Žπ‘Ÿπ‘”π‘’π‘Ÿ 𝑁𝐴 -> hitting limits
  • 5. Pierre Lartigues Field , 3D Plus USA Flash Memory Summit 2012 Santa Clara, CA -
  • 6. Current common packaging Developing, TSV approach: More interconnects and shorter Interconnects -> Higher bit rate Disadvantages of thinner longer wire interconnect: 1. Insufficient bandwidth, slow rise/fall pulse 2. Skin effect, Dielectric loss 3. Cross-talk 4. Low Bit-rate (B) between memory and CPU β†’ Memory wall Bit-rate 𝐡 𝛼 𝐴/𝑙2 David Miller, Opt. Inter., 1997, Proc IEEE June 2000 Currently CPUs are faster but memory to CPU Bit-transfer rate is slow. We want higher performance…
  • 8. In monolithic approach active layers and devices on them are built sequentially in bottom up approach on top of a wafer. Pros: The vertical interconnects are formed between layers rather than chips, using vias in the π‘›π‘š rather than πœ‡π‘š range. Cons: High quality active layer isolation need to be formed between each active layers. 2. Crystallinity of upper layers is often imperfect. 3. This approach works only if polycrystalline silicon could be used for making devices. Reference: 3D Integration for VLSI Systems Chuan Seng Tan, Kuan-Neng Chen, Steven J. Koester οƒ˜ Better way : Stack chips with devices
  • 9. 1. Temporary bonding needed before forming via, for thinning by CMP and debonding and bonding again is a very complex and delicate process. 2. Thermal management issue: β€’ Stacking of memory chips alone does not produce heat issues, but integration with logic Chip will have issues as neighboring memory chip will get high heat from adjacent Logic chip. β€’ Copper via might help themselves will conduct out some heat but may not be enough. β€’ Low cost thermally aware via design is necessary 3. Copper reacts with Si, so passivation layer must be formed in the via walls before filling in via with Cu, which is challenging 4. Stress is another issue: Thermal expansively: Cu - 16.7ppm/C W – 6-8 ppm/C Si – 2.6 ppm/C -> Stress development on wafer when TSVs expands.
  • 10. β€’ Thinned wafer/die handling and bow management β€’ Si wafer cracking β€’ Supply of micro-bump between stacks. β€’ Defect visibility, measurement sensitivity and identification β€’ Complexity of the system, hidden structures β€’ Design Test etc. οƒ˜ Reliable non-destructive metrology is needed
  • 11. οƒ˜ Excellent tool for distinguishing and quantifying crystallinity of silicon surface οƒ˜ Crystalline silicon has very sharp peaks, such as the one centered at ~ 520 cm-1 οƒ˜ Also, Micro-Raman spectroscopy: useful to detect local stress on surface
  • 12. Thesis: Keshab Raj Paudel, University of Missouri 𝑋𝑃𝑆, π‘ˆπ‘ƒπ‘†: 𝐸 𝐡 = β„Žπœˆ βˆ’ 𝐸 𝐾 βˆ’ π‘Š 𝐴𝐸𝑆: 𝐾. 𝐸. = (𝐸 πΎβˆ’πΈπΏ1) βˆ’ 𝐸23 Wide scan of 10nm Au nanoparticle on Silicon surface Angle resolved method: -> Sensitive to nm scale layers οƒ˜ Chemical analysis of surface οƒ˜ Quantitative analysis
  • 13. Dissertation: Keshab Raj Paudel, University of Missouri οƒ˜ Very sensitive and fast compared to dispersive IR absorption technique. οƒ˜ Great for surface chemical analysis. οƒ˜ Observation of Si-O bands are very intense. C-H, C-C etc. modes characterize/identify materials on Silicon wafer Natural Diamond
  • 14. Source: OLYMPUS 3D Metrology using IR Microscopy A non-destructive imaging technique β€’ In-line monitoring of the 3D bonding process: β€’ Overlay alignment offset monitoring β€’ Tracking process variations β€’ Post bond defect inspection and review οƒ˜ Confocal NIR microscopy using interferometry looks further Promising and is among already available technologies and offers has new possibilities Limit: Can see only up to πŸ–πŸŽπŸŽ ππ’Ž inside
  • 15. David Bernard, John Tingay et. al. "THE X-RAY METROLOGY OF TSVS AND WAFER BUMPS” - Nordson DAGE, Feb 3, 2015 Oblique view x-ray image of 10 x 100 ΞΌm TSVs. The lighter areas within the TSVs are voids. X-ray image of 50 ΞΌm diameter wafer bumps. Top-down image. Computer Tomography
  • 16. Can limit X-ray beam from 0.1πœ‡π‘š π‘‘π‘œ 100πœ‡π‘š for higher resolution X βˆ’ ray imaging Working: Total External Reflection, Critical incident angle, πœƒπ‘ π‘Ÿπ‘Žπ‘‘π‘–π‘Žπ‘› = 002 βˆ— 𝜌 ( 𝑔 π‘π‘š3)/𝐸(π‘˜π‘’π‘‰) Ref.: X-Ray Spectrometry: Recent Technological Advances edited by Kouichi Tsuji, Jasna Injuk, RenΓ© Van Grieken οƒ˜ Higher resolution than standard techniques
  • 17. οƒ˜ Ultrasonic transducer to scan the wafer for defects that modify the reflection of sound waves. οƒ˜ Excels at finding voids and cracks, Cons: Wafer needs to be immersed in a sound-conducting liquid, usually distilled water. οƒ˜ This requires a cleaning step after the sonic scan is generated, while limiting application to wafers which will not be contaminated by immersion. οƒ˜ Relatively coarse with lateral resolution. SEMICONDUCTOR International , August 2009 Acoustic image of a crack at the bond interface in an Au-Si bonded wafer pair.
  • 18. Phase difference: Ξ“ = 2πœ‹ 𝑛1 π‘₯1 βˆ’ 𝑛2 π‘₯2 πœ† Light source To spectrometer οƒ˜ Non-destructive method οƒ˜ Based on spectral reflectometry οƒ˜ Several theoretical models (common: Rigorous Coupled Wave Theory) οƒ˜ Highly promising Source: IBM, ECTC 2014
  • 19. Top CD and Depth High Precision Allows Effective Control of Etch Rate and Uniformity Source: IBM, ECTC 2014
  • 20. Marvin B. Klein, W.E. Moerner et al., Optics Communications 162, 1999. 79–84 O. Ostroverkhova, W.E. Moerner et al., Chemical Reviews, Vol. 104, No. 7, 3267-3314, 2004 Schematic diagram of a laser ultrasonic receiver based on two-wave mixing PR material: PVK:7-DCST:BBP:C60 οƒ˜ Major Advantage: Insensitive to fluctuations in the frequency of the laser οƒ˜ Minimum detectable displacement: πœΉπ’π’Šπ’Ž π’Šπ’…π’†π’‚π’ = 𝟐. πŸ• Γ— πŸπŸŽβˆ’πŸ– π’π’Ž οƒ˜ Varieties of PR materials developed thus far. οƒ˜ Inexpensive experimental set up for R&D οƒ˜ Dynamic hologram οƒ˜ Strong ties with related people
  • 21. Light: Science & Applications (2012) 1, e36; doi:10.1038/lsa.2012.36 www.nature.com/lsa
  • 22. Driving factors: οƒ˜ High density, multi-wavelength low-power photonics connectors -> Enabler for Tbps applications οƒ˜ High density photonics in 3DI-> Extreme 3D Source: Emerging Technologies and Market Trends of Silicon Photonics – S.BernabΓ© ECTC 2014
  • 23. Knots and bolts for optical interconnects 1. Lasers 2. Waveguides – Si, cladded with SiO2 3. Ring resonators 4. Diode detectors (MSM, PIN III-V detectors) 5. Optical amplifiers ( e.g.. Erbium booster) Challenges: Metrology again 1. Laser mode validation using external mode analysis tools such as scanning FB Interferometer (which are commercially available, I have experience on such tools) 2. Pulse analysis using high speed spectrum analyzers ( e.t. Tektronix spectrum analyzer) Check for stretch effect and intensity loss. Bit Error Rate (BER). 3. Test against micro bends and loss. – Challenging when waveguides are in the bulk of 3D Geometry (good thing is that Si is transparent to IR), easier only in 2D geometry
  • 24. Scanning Fabry-Perot Interferometer Measures Laser linewidth as well. Advanced Optics Lab, University of Missouri , Columbia Tool not shown resonance condition πœ† = 2𝑑 π‘š
  • 25. οƒ˜ Speed becomes infinite in ENZ media. Or οƒ˜ Waves inside ENZ materials have very long wavelength and essentially have a uniform phase throughout the propagation distance. οƒ˜ Connect the two waveguides by an ENZ material, the coupling is better if the channel is narrower ! οƒ˜ Metal clad waveguides near their cutoff frequency can mimic the ENZ material in the sense that the effective mode index can approach zero. Science, Vol. 340 no. 6130 pp. 286-287, 2013 𝚫 Γ— 𝑬 = π’ŠπŽππ‘― 𝚫 Γ— 𝑯 = 𝟎 𝚫 𝟐 𝑬 = 𝟏 𝒄 𝟐 (𝝏 𝟐 𝑬/𝝏𝒕 𝟐 )
  • 26. οƒ˜ 3DI manufacturing: rapidly developing and promising with TSV οƒ˜ Existing metrology tools: not sufficient for TSV technology οƒ˜ Optical scatterometry: several variants/models, need further development οƒ˜ Interferometric technique with PR materials: Promising opportunity for metrology development οƒ˜ Hybrid photonic integration: Progressing and it is the future of high speed integration -> careful optical studies/tests needed