The document discusses a six-step process for characterizing high-speed serial communication links at 1Gbps or higher to measure, identify, and eliminate sources of clock and data jitter. The steps include quantifying random and deterministic jitter, analyzing amplitude noise histograms, comparing eye diagrams to masks, separating jitter types and components, and diagnosing the root causes of jitter by examining the frequency domain. The goal is to understand different types of jitter, find their causes, and eliminate effects to ensure reliable data transmission.
Study of Compensation of Variable Delay in Communication Link Using Communica...ijsrd.com
With growing technology, number of control system elements is increasing. So, it is not possible to place entire control system at a same place. Therefore, separate control elements connected by a communication link are required, it introduces delay. This delay is either constant or random in nature depending on communication link. This delay destabilizes the overall system and can be compensated using smith predictor. But smith predictor is only applicable to constant delay communication links. In this paper, communication disturbance observer (CDOB) and network disturbance (ND) have been introduced to compensate variable delay in communication link.
FPGA based Efficient Interpolator design using DALUT Algorithmcscpconf
Interpolator is an important sampling device used for multirate filtering to provide signal processing in wireless communication system. There are many applications in which sampling rate must be changed. Interpolators and decimators are utilized to increase or decrease the sampling rate. In this paper an efficient method has been presented to implement high speed and area efficient interpolator for wireless communication systems. A multiplier less technique is used which substitutes multiplyand-accumulate operations with look up table (LUT) accesses. Interpolator has been implemented using Partitioned distributed arithmetic look up table (DALUT) technique. This technique has been used to take an optimal advantage of embedded LUTs of the target FPGA. This method is useful to enhance the system performance in terms of speed and area. The proposed interpolator has been designed using half band poly phase FIR structure with Matlab, simulated with ISE, synthesized with Xilinx Synthesis Tools (XST) and implemented on Spartan-3E and Virtex2pro device. The proposed LUT based multiplier less approach has shown a maximum operating frequency of 92.859 MHz with Virtex Pro and 61.6 MHz with Spartan 3E by consuming considerably less resources to provide cost effective solution for wireless communication systems.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Study of Compensation of Variable Delay in Communication Link Using Communica...ijsrd.com
With growing technology, number of control system elements is increasing. So, it is not possible to place entire control system at a same place. Therefore, separate control elements connected by a communication link are required, it introduces delay. This delay is either constant or random in nature depending on communication link. This delay destabilizes the overall system and can be compensated using smith predictor. But smith predictor is only applicable to constant delay communication links. In this paper, communication disturbance observer (CDOB) and network disturbance (ND) have been introduced to compensate variable delay in communication link.
FPGA based Efficient Interpolator design using DALUT Algorithmcscpconf
Interpolator is an important sampling device used for multirate filtering to provide signal processing in wireless communication system. There are many applications in which sampling rate must be changed. Interpolators and decimators are utilized to increase or decrease the sampling rate. In this paper an efficient method has been presented to implement high speed and area efficient interpolator for wireless communication systems. A multiplier less technique is used which substitutes multiplyand-accumulate operations with look up table (LUT) accesses. Interpolator has been implemented using Partitioned distributed arithmetic look up table (DALUT) technique. This technique has been used to take an optimal advantage of embedded LUTs of the target FPGA. This method is useful to enhance the system performance in terms of speed and area. The proposed interpolator has been designed using half band poly phase FIR structure with Matlab, simulated with ISE, synthesized with Xilinx Synthesis Tools (XST) and implemented on Spartan-3E and Virtex2pro device. The proposed LUT based multiplier less approach has shown a maximum operating frequency of 92.859 MHz with Virtex Pro and 61.6 MHz with Spartan 3E by consuming considerably less resources to provide cost effective solution for wireless communication systems.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
IOSR Journal of Mechanical and Civil Engineering (IOSR-JMCE) is a double blind peer reviewed International Journal that provides rapid publication (within a month) of articles in all areas of mechanical and civil engineering and its applications. The journal welcomes publications of high quality papers on theoretical developments and practical applications in mechanical and civil engineering. Original research papers, state-of-the-art reviews, and high quality technical notes are invited for publications.
The International Journal of Engineering and Science (The IJES)theijes
The International Journal of Engineering & Science is aimed at providing a platform for researchers, engineers, scientists, or educators to publish their original research results, to exchange new ideas, to disseminate information in innovative designs, engineering experiences and technological skills. It is also the Journal's objective to promote engineering and technology education. All papers submitted to the Journal will be blind peer-reviewed. Only original articles will be published.
30 9762 extension paper id 0030 (edit i)IAESIJEECS
This paper deals with border distortion effect at starting and ending of finite signal by proposing sliding window technique and basic extension mode implementation. Single phase of transient and voltage sag is chosen to be analyzed in wavelet. The signal which being used for the analysis is simulated in Matlab 2017a. Disturbance signal decomposes into four level and Daubechies 4 (db4) has been chosen for computation. The proposed technique has been compared with conventional method which is finite length power disturbance analysis. Simulation result revealed that the proposed smooth-padding mode can be successfully minimized the border distortion effect compared to the zero-padding and symmetrization
A Novel Algorithm on Wavelet Based Robust Invisible Digital Image Watermarkin...IJERA Editor
This paper presents a new algorithm on waveletbased robust and invisible digital image watermarking for multimedia security. The proposed algorithm has been designed, implemented and verified using MATLAB R2014a simulation for both embedding and extraction of the watermark and the results of which shows significant improvement in performance metrics like PSNR, SSIM, Mean Correlation, MSE than the other existing algorithms in the current literature. The cover image considered here in our algorithm is of the size (256x256) and the binary watermark image size is taken as (16x16).
“FIELD PROGRAMMABLE DSP ARRAYS” - A NOVEL RECONFIGURABLE ARCHITECTURE FOR EFF...sipij
Digital Signal Processing functions are widely used in real time high speed applications. Those functions
are generally implemented either on ASICs with inflexibility, or on FPGAs with bottlenecks of relatively
smaller utilization factor or lower speed compared to ASIC. The proposed reconfigurable DSP processor is
redolent to FPGA, but with basic fixed Common Modules (CMs) (like adders, subtractors, multipliers,
scaling units, shifters) instead of CLBs. This paper introduces the development of a reconfigurable DSP
processor that integrates different filter and transform functions. The switching between DSP functions is
occurred by reconfiguring the interconnection between CMs. Validation of the proposed reconfigurable
architecture has been achieved on Virtex5 FPGA. The architecture provides sufficient amount of flexibility,
parallelism and scalability.
This project describes a novel architecture based on Recursive Running Sum (RRS) filter implementation for wire and wireless data processing. UARTs are used for asynchronous serial data communication between remote embedded systems. If physical channel is noisy then, serial data bits get corrupted during transmission. The UART core described here, utilizes recursive running sum filter to remove noisy samples. Input data signal is directly sampled with system clock and samples are accumulated over a window size. The window size is user programmable and it should be set to one tenth of required bit period. The intermediate data bit is decoded using magnitude comparator. The advantage of this architecture is that baud rate is decided by the window size so there is no need of any external “timer module” which is normally required for standard UARTs. The Recursive Running Sum (RRS) filter architecture with programmable window size of M is designed and modules are implemented with VHDL language. This project implementation includes many applications in wireless data communication Systems like RF, Blue tooth, WIFI, ZigBee wireless sensor applications. Total coding written in VHDL language. Simulation in Modelsim Simulator, Synthesis done by XILINX ISE 9.2i. Synthesis result is verified by the Chipscope. Input signal given from the keyboard and output is seen by the help of HyperTerminal.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
An fpga implementation of the lms adaptive filter eSAT Journals
Abstract This paper brings out implementation of Least Mean Square (LMS) algorithm using two different architectures. The implementations are made on Xilinx Virtex–4 FPGA as part of realization of an Active Vibration Control system. Both fixed point and floating point data representations are considered. A comparison between the two is brought out on the basis of a Finite State Machine (FSM) model suitable for both fixed & floating point implementations. The floating point LMS algorithm in VHDL (Very High Speed Integrated Circuit (VHSIC) Hardware Description Language), uses the Intellectual Property (IP) cores available from Xilinx Inc. Results from the two architectures with respect to area as well as performance clearly shows floating point implementation to emerge as the better option in all respects. Index Terms: Least Mean Square Algorithm, Field programmable gate arrays (FPGA), floating point IP cores, Finite State Machine, Active Vibration Control.
Glitch Analysis and Reduction in Digital CircuitsVLSICS Design
Low Power Circuit Design has become very crucial in today’s era of modern portable consumer
gadgets. For CMOS combinational circuits, the reduction of dynamic power dissipation is very
important. A signal transition can be of two types: a functional transition and glitch. Before
reaching the steady state, a signal might go through several state changes which are called
glitches. As they dissipate 20-70% of total power dissipation, glitch is needed to be eliminated for
low power design.
PTotal=PStatic +Pdynamic (1)
PTotal=PSwitching+PShort-Circuit+ Pleakage (2)
Total Power dissipation consists of mainly dynamic power dissipation and static power
dissipation, further these are divided into switching power dissipation, leakage power dissipation,
short circuit power dissipation. Dynamic power dissipation is a major source of leakage power,
which is directly proportional to the number of signal transitions(1-0 and 0-1) in a digital circuit.
Switching power dissipation (Pswitching) is directly proportional to switching activity(a),load
capacitance(Cload), Voltage supply (Vdd) and clock frequency( fclk) as show
The "top down" approach emphasizes readers bringing meaning to text based on their experiential background and interpreting text based on their prior knowledge (whole language).
12 Months of Awesome (Content) for Socially Responsible BusinessesAndrew Boardman
Having worked with dozens of socially responsible businesses
over the years, we have learned that having access to great,
regular and informed content is key to your communications
success. And content is more important than ever in
connecting with prospective and current customers and
clients.
Your business blog and social media channels make up a
crucial part of your marketing and communications strategy.
Please use this calendar to outline or enhance your content
strategy and keep on top of your marketing goals for the
remainder of 2015 and the first eight months of 2016.
IOSR Journal of Mechanical and Civil Engineering (IOSR-JMCE) is a double blind peer reviewed International Journal that provides rapid publication (within a month) of articles in all areas of mechanical and civil engineering and its applications. The journal welcomes publications of high quality papers on theoretical developments and practical applications in mechanical and civil engineering. Original research papers, state-of-the-art reviews, and high quality technical notes are invited for publications.
The International Journal of Engineering and Science (The IJES)theijes
The International Journal of Engineering & Science is aimed at providing a platform for researchers, engineers, scientists, or educators to publish their original research results, to exchange new ideas, to disseminate information in innovative designs, engineering experiences and technological skills. It is also the Journal's objective to promote engineering and technology education. All papers submitted to the Journal will be blind peer-reviewed. Only original articles will be published.
30 9762 extension paper id 0030 (edit i)IAESIJEECS
This paper deals with border distortion effect at starting and ending of finite signal by proposing sliding window technique and basic extension mode implementation. Single phase of transient and voltage sag is chosen to be analyzed in wavelet. The signal which being used for the analysis is simulated in Matlab 2017a. Disturbance signal decomposes into four level and Daubechies 4 (db4) has been chosen for computation. The proposed technique has been compared with conventional method which is finite length power disturbance analysis. Simulation result revealed that the proposed smooth-padding mode can be successfully minimized the border distortion effect compared to the zero-padding and symmetrization
A Novel Algorithm on Wavelet Based Robust Invisible Digital Image Watermarkin...IJERA Editor
This paper presents a new algorithm on waveletbased robust and invisible digital image watermarking for multimedia security. The proposed algorithm has been designed, implemented and verified using MATLAB R2014a simulation for both embedding and extraction of the watermark and the results of which shows significant improvement in performance metrics like PSNR, SSIM, Mean Correlation, MSE than the other existing algorithms in the current literature. The cover image considered here in our algorithm is of the size (256x256) and the binary watermark image size is taken as (16x16).
“FIELD PROGRAMMABLE DSP ARRAYS” - A NOVEL RECONFIGURABLE ARCHITECTURE FOR EFF...sipij
Digital Signal Processing functions are widely used in real time high speed applications. Those functions
are generally implemented either on ASICs with inflexibility, or on FPGAs with bottlenecks of relatively
smaller utilization factor or lower speed compared to ASIC. The proposed reconfigurable DSP processor is
redolent to FPGA, but with basic fixed Common Modules (CMs) (like adders, subtractors, multipliers,
scaling units, shifters) instead of CLBs. This paper introduces the development of a reconfigurable DSP
processor that integrates different filter and transform functions. The switching between DSP functions is
occurred by reconfiguring the interconnection between CMs. Validation of the proposed reconfigurable
architecture has been achieved on Virtex5 FPGA. The architecture provides sufficient amount of flexibility,
parallelism and scalability.
This project describes a novel architecture based on Recursive Running Sum (RRS) filter implementation for wire and wireless data processing. UARTs are used for asynchronous serial data communication between remote embedded systems. If physical channel is noisy then, serial data bits get corrupted during transmission. The UART core described here, utilizes recursive running sum filter to remove noisy samples. Input data signal is directly sampled with system clock and samples are accumulated over a window size. The window size is user programmable and it should be set to one tenth of required bit period. The intermediate data bit is decoded using magnitude comparator. The advantage of this architecture is that baud rate is decided by the window size so there is no need of any external “timer module” which is normally required for standard UARTs. The Recursive Running Sum (RRS) filter architecture with programmable window size of M is designed and modules are implemented with VHDL language. This project implementation includes many applications in wireless data communication Systems like RF, Blue tooth, WIFI, ZigBee wireless sensor applications. Total coding written in VHDL language. Simulation in Modelsim Simulator, Synthesis done by XILINX ISE 9.2i. Synthesis result is verified by the Chipscope. Input signal given from the keyboard and output is seen by the help of HyperTerminal.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
An fpga implementation of the lms adaptive filter eSAT Journals
Abstract This paper brings out implementation of Least Mean Square (LMS) algorithm using two different architectures. The implementations are made on Xilinx Virtex–4 FPGA as part of realization of an Active Vibration Control system. Both fixed point and floating point data representations are considered. A comparison between the two is brought out on the basis of a Finite State Machine (FSM) model suitable for both fixed & floating point implementations. The floating point LMS algorithm in VHDL (Very High Speed Integrated Circuit (VHSIC) Hardware Description Language), uses the Intellectual Property (IP) cores available from Xilinx Inc. Results from the two architectures with respect to area as well as performance clearly shows floating point implementation to emerge as the better option in all respects. Index Terms: Least Mean Square Algorithm, Field programmable gate arrays (FPGA), floating point IP cores, Finite State Machine, Active Vibration Control.
Glitch Analysis and Reduction in Digital CircuitsVLSICS Design
Low Power Circuit Design has become very crucial in today’s era of modern portable consumer
gadgets. For CMOS combinational circuits, the reduction of dynamic power dissipation is very
important. A signal transition can be of two types: a functional transition and glitch. Before
reaching the steady state, a signal might go through several state changes which are called
glitches. As they dissipate 20-70% of total power dissipation, glitch is needed to be eliminated for
low power design.
PTotal=PStatic +Pdynamic (1)
PTotal=PSwitching+PShort-Circuit+ Pleakage (2)
Total Power dissipation consists of mainly dynamic power dissipation and static power
dissipation, further these are divided into switching power dissipation, leakage power dissipation,
short circuit power dissipation. Dynamic power dissipation is a major source of leakage power,
which is directly proportional to the number of signal transitions(1-0 and 0-1) in a digital circuit.
Switching power dissipation (Pswitching) is directly proportional to switching activity(a),load
capacitance(Cload), Voltage supply (Vdd) and clock frequency( fclk) as show
The "top down" approach emphasizes readers bringing meaning to text based on their experiential background and interpreting text based on their prior knowledge (whole language).
12 Months of Awesome (Content) for Socially Responsible BusinessesAndrew Boardman
Having worked with dozens of socially responsible businesses
over the years, we have learned that having access to great,
regular and informed content is key to your communications
success. And content is more important than ever in
connecting with prospective and current customers and
clients.
Your business blog and social media channels make up a
crucial part of your marketing and communications strategy.
Please use this calendar to outline or enhance your content
strategy and keep on top of your marketing goals for the
remainder of 2015 and the first eight months of 2016.
Ijciss1 april2612 A STUDY ON CELLULAR SERVICE INDUSTRY ON ITS SERVICE QUALITY...IJMR Journal
The objectives of this paper were to explore reasons why consumers prefer a specific mobile service and to explore the relationship between Service Quality, Customer Satisfaction and Brand Loyalty. The cellular service providers are using different sales promotional methods to attract the customers towards them. For further enhancement, to measure the Customers’ Satisfaction and Service Quality towards Brand Loyalty of cellular service is important. The survey instruments used in the present study to measure Brand Loyalty were Service Quality, Price, Product Quality, Promotional Quality and Customer Satisfaction. Thus the structural equation modeling approach was necessary in order to examine the variables. The findings revealed that reliability, responsiveness in service quality, reasonable price and customer satisfaction leads to brand loyalty towards cellular communication providers. The researcher suggests that proper promotional offer with right service at the right time and enhanced product quality to make the customer satisfied and loyal to the service providers.
Keywords: Service Quality, Price, Product quality, Promotional quality, Customer satisfaction, Service/Brand loyalty.
Design for Learning: The Future of the Web (Well, for 5 Years)Andrew Boardman
Over the next few years, websites will change from validation tools to learning platforms. Through your website, people will want to learn from your business, connect with your ideas, and develop strong relationships. Remarkable content, coupled with smart design, will help make those connections. The best communication professionals will help drive those connections and must be prepared for the changes immediately ahead. The talk will discuss a brief history of the web, how content is changing online, why we talk about learning, and where design and communications will be most impactful in the next few years.
All words belong to categories called word classes (or parts of speech) according to the part they play in a sentence. The main word classes in English are:
- Noun
- Verb
- Adjective
- Adverb
- Pronoun
- Conjunction
- Determiner
- Exclamation
- Preposition
AN ANALYSIS OF CHILD ABUSE IN INDIAN SCENARIOIJMR Journal
Public conscience is not outraged, despite occasional investigative media reporting and social action litigation in appellate courts in labour-surplus economy and chronic unemployment which provide passport for ruthless exploitation. According to Precht, the promotion of the basic rights of persona and nations will be successful if they will be considered from the perspective of the poor people. Among factors contributing to child labour, the important are rapid population growth, adultery unemployment, bad working conditions, lack of minimum wages, exploitation of workers, low standard of living, low quality of education, lack of legal provisions and enforcement, low capacity of institutions, gender discrimination conceptual thinking about childhood. Mindset of the people can be changed by imparting value based education and culture.
Scot-Tech Engagement's Cyber Security Conference for Scottish Business, held 30th April 2015, Edinburgh. For more information contact ray@scot-tech.com.
Please note further presentations will be added once speakers have approved
ETHICAL BUSINESS PRACTICES: A KEY TO SUCCESSFUL EXPORT TRADEIJMR Journal
The term ethics in simple layman’s words can be described as moral philosophy. The dictionary however says that the word “ethics” is derived from the Greek word “Ethikos” meaning customs or character. Since ethics is described as moral philosophy it could be elaborated by calling it a branch of philosophy and is considered a normative science because it is concerned with the norms of human conduct, as distinguished from formal sciences such as mathematics and logic, physical sciences such as chemistry and empirical sciences such as economics or psychology. The ethical practices in conducting the business may sounds to be difficult but in long run its fruits can be reaped by generations to come. In this paper, “Ethical Business Practices: A Key to successful export trade” an effort has been made to highlight the business practices at Tynor Orthotics Ltd having worldwide acceptability of the products which is the basic requirement for sustainability in the today’s global economy. The primary data has been collected directly through discussions with the officials related to Tynor and the secondary data has been collected from reports of Tynor and website. The ethical business practices followed at the Tynor has contributed a lot in the world wide acceptability of its products.
Scotland's only conference devoted to ITSM (IT Service Management) attended by over 150 IT professionals. This event was held 25th October 2016, Edinburgh.
DELAY ERROR WITH META-STABILITY DETECTION AND CORRECTION USING CMOS TRANSMISS...VLSICS Design
The new technologies are giving the advance systems which are capable to perform multiple operations simultaneously. This all is possible by the scaling technology where the overall chip size get reduced but due to manufacturing and fabrication defects, certain design uncertainty arises thereby affecting the transistor performance by timing related effect. The robust circuit where sufficient margins are given sometime is nothing but a wastage of power to overcome this, hybrid technique called Razor was innovated which scaled the voltage dynamically and automatically detect and correct the timing related defects. This paper proposed a new design for the razor flip flop with CMOS transmission logic. The traditional design used the dynamic logic approach which has the drawback of threshold voltage attenuation which is removed by CMOS transmission logic and the transparency of the logic data at input and output is highly achieved. The overall purpose for such design is to reduce the power and delay of the circuit which is reduced by 0.6mW and 12.11ns respectively and thus increased the overall performance. The complexity of
the circuit is also reduced. The analyses of the circuit is done using Cadence virtuoso tool with 45n technology.
An approach to Measure Transition Density of Binary Sequences for X-filling b...IJECEIAES
Switching activity and Transition density computation is an essential stage for dynamic power estimation and testing time reduction. The study of switching activity, transition densities and weighted switching activities of pseudo random binary sequences generated by Linear Feedback shift registers and Feed Forward shift registers plays a crucial role in design approaches of Built-In Self Test, cryptosystems, secure scan designs and other applications. This paper proposed an approach to find transition densities, which plays an important role in choosing of test pattern generator We have analyze conventional and proposed designs using our approache, This work also describes the testing time of benchmark circuits. The outcome of this paper is presented in the form of algorithm, theorems with proofs and analyses table which strongly support the same. The proposed algorithm reduces switching activity and testing time up to 51.56% and 84.61% respectively.
Performance Analysis of IEEE 802.15.4 Transceiver System under Adaptive White...IJECEIAES
Zigbee technology has been developed for short range wireless sensor networks and it follows IEEE 802.15.4 standard. For such sensors, several considerations should be taken including; low data rate and less design complexity in order to achieve efficient performance considering to the transceiver systems. This research focuses on implementing a digital transceiver system for Zigbee sensor based on IEEE 802.15.4. The system is implemented using offset quadrature phase shift keying (OQPSK) modulation technique with half sine pulse-shaping method. Direct conversion scheme has been used in the design of Zigbee receiver in order to fulfill the requirements mentioned above. System performance is analyzed considering to BER when it encountered adaptive white Gaussian noise (AWGN), besides showing the effect of using direct sequence spread spectrum (DSSS) technique.
Improvement in Error Resilience in BIST using hamming codeIJMTST Journal
In the current scenario of IP core based SoC, to test the CUT we need to communication link between Circuit Under Test and ATPG, so before applying to actual DUT. If there is a problem with this link, there may be a lip in bit of test data. Compared to original test data, if there is a bit lip in the original data, the codeword may change and hence the decompressed data will have a large number of bit deviation. This deviation in bits can severely degrade the test quality and overall fault coverage which may affect yield. The error resilience is the capability of the test data to resist against such bit lips. Here in this paper, the earlier methods of error resilience is compared and a Hamming code based error resilience technique is proposed to improve the error resilience capacity of compressed test data. This method is applied on Huffman code based compressed test data of widely used ISCAS benchmark circuits. The fault coverage measurement results show the effectiveness of the proposed method. The basic goal here is to survey the effect of bit lips on fault coverage and prepare a platform for further development in this avenue.
DSP Based Implementation of Scrambler for 56kbps ModemCSCJournals
Scrambler is generally employed in data communication systems to add redundancy in the transmitted data stream so that at the receiver end, timing information can be retrieved to aid the synchronization between data terminals. Present paper deals with simulation and implementation of the scrambler for 56Kbps voice-band modem. Scrambler for the transmitter of 56kbps modem was chosen as a case study. Simulation has been carried out using Simulink of Matlab. An algorithm for the scrambling function has been developed and implemented on Texas Instrument’s based TMS320C50PQ57 Digital Signal Processor (DSP). Signalogic DSP software has been used to compare the simulated and practical results.
Turbo codes are error-correcting codes with performance that is close to the
Shannon theoretical limit (SHA). The motivation for using turbo codes is
that the codes are an appealing mix of a random appearance on the channel
and a physically realizable decoding structure. The communication systems
have the problem of latency, fast switching, and reliable data transfer. The
objective of the research paper is to design and turbo encoder and decoder
hardware chip and analyze its performance. Two convolutional codes are
concatenated concurrently and detached by an interleaver or permuter in the
turbo encoder. The expected data from the channel is interpreted iteratively
using the two related decoders. The soft (probabilistic) data about an
individual bit of the decoded structure is passed in each cycle from one
elementary decoder to the next, and this information is updated regularly.
The performance of the chip is also verified using the maximum a posteriori
(MAP) method in the decoder chip. The performance of field-programmable
gate array (FPGA) hardware is evaluated using hardware and timing
parameters extracted from Xilinx ISE 14.7. The parallel concatenation offers
a better global rate for the same component code performance, and reduced
delay, low hardware complexity, and higher frequency support.
A Broadband Wireless Access technology known as
Worldwide Interoperability for Microwave Access (WiMAX) is
based on IEEE 802.16 standards. It uses orthogonal frequency
division multiple accesses (OFDMA) as one of its multiple access
technique. Major design factors of OFDMA resource allocation are
scheduling and burst allocation. To calculate the appropriate
dimensions and location of each user’s data so as to construct the
bursts in the downlink subframe, is the responsibility of burst
allocation algorithm. Bursts are calculated in terms of number of
slots for each user. Burst Allocation Algorithm is used to overcome
the resource wastage in the form of unused and unallocated slots per
frame. It affects the Base station performance in mobile WiMAX
systems. In this Paper, HOCSA (Hybrid One Column Striping with
Non Increasing Area) algorithm is proposed to overcome frame
wastage. HOCSA is implemented by improving eOCSA algorithm
and is evaluated using MATLAB. HOCSA achieves significant
reduction of resource wastage per frame, leading to more
exploitation of the WiMAX frame.
COMPARATIVE ANALYSIS OF SIMULATION TECHNIQUES: SCAN COMPRESSION AND INTERNAL ...IJCI JOURNAL
With advancement in technology, the feature size of transistors is shrinking and the transistor count in a circuit design is exponentially increasing. As a result, it is hard to control and observe internal nodes leading to complexity in locating and debugging faults specially for sequential circuits. Design for Testability (DFT) provides a way for fault detection of the circuit under test in less simulation duration with little increase in area. Many techniques are proposed under DFT for pattern simulation. In this paper, we have compared two such pattern simulation techniques namely scan compression and internal scan. The experiment is performed on different benchmark circuits, it is observed the simulation time is significantly reduced with increased coverage and a little area overhead.
Characterizing High-Speed Serial Communications Links Requires Some Analog Savvy_wiht_Figures
1. Characterizing High-Speed Serial Communications Links
Requires Some Analog Savvy
A six-step process helps measure, identify, and eliminate clock and data jitter on those
blazing serial signals.
Dec 1, 2008Hamed M. Sanogo Electronic Design
As serial-data standards go from fast to very fast, designers must devote a greater amount of
time to the analog features of those high-speed signals. It’s no longer enough to remain in
the digital domain with ones and zeros. To find and correct conditions that lead to potential
problems—and thereby prevent those problems from showing up in the field—designers
must check the parametric realm of their designs. Signal integrity (SI) engineers have to
mitigate or eliminate the effects of timing jitter on system performance. The following
discussion offers a simple and practical procedure for characterizing high-speed serial data
links at 1Gbps and beyond.
The characterization of a high-speed serial link depends on the ability of the SI engineer to
find, understand, and solve serious jitter problems. In this discussion, we assume that the
clock and data recovery (CDR) block of the PHY (physical layer) or SERDES (serializer-
deserializer) device complies with the standards applicable to that device. In a serial
communication system, the CDR recovers the clock signal from the data stream. Therefore,
a key operation is to extract data from the serial data stream and synchronize it with the
data-transmitter clock.
2. The transmitter always contributes some jitter to the recovered clock, but let’s assume that
contribution to be minimal. For the purpose of simplification, we’ll assume any jitter seen
on the recovered clock to have been coupled either onto the link in the cable (as EMI) or
within the PCB (as cross-talk).
Jitter transfer, jitter tolerance, and jitter generation are important measures, but they apply
more to PHY and SERDES devices than to the testing of system channels. Imagine the
devices used in our design meet all device-level compliance testing, and we can focus on the
complete system as we find a way to reliably capture serial data at the receiver. We’ll look at
system-channel characterization rather than device characterization. Such a channel
consists of the transmitter PHY, FR4 (PCB material), connector, shielded cable, connector,
FR4, and receiver PHY (Figure 1).
The embedded telecomm card, a mixed-signal board used to collect many of the
measurements in this article, is part of a “radio unit.” The radio unit connects to the base
station via a Common Public Radio Interface (CPRI), a new standard for communications
between a base station and a radio unit. One physical layer in the CPRI includes the radio
data (IQ data) as well as management, control, and synchronization information. For the
application described in this article, the CPRI was specified to run on a serial link at
1.2288Gbps. This serial link was then characterized and measured to illustrate the jitter
tests.
Jitter–Understanding Its Make-Up
The most important steps, therefore, in achieving the performance specified for a high-
speed serial-communications interface include understanding jitter, finding its causes, and
eliminating some of its effects. Although this article is not a tutorial on the topic of jitter, it’s
hard to talk about testing a serial communication link without saying at least a word or two
about jitter. Accordingly, the discussion in this section is directed to those who are new to
the subject.
3. Jitter is defined as the variation of a signal edge from its ideal position in time. More
specifically, jitter is the misalignment of the significant edges of a digital signal from their
ideal positions in time (Figure 2). Jitter can also be viewed as an unwanted phase
modulation of the digital signal. The SI engineer must understand: a receiver that meets the
serial-link data rate but does not meet its jitter specification may not operate reliably. Jitter
characterization is therefore essential in guaranteeing an acceptable bit error rate (BER) for
the system. Jitter can affect timing margins, synchronization, and cause a long list of other
problems.
Viewed as deviations of output transitions from their ideal positions, jitter is an important
performance measure for both the clock and data signals of a serial link. The continuous
incremental addition of jitter leads eventually to data errors. Remember, any time-domain
measurement taken on a hardware system is only as good as the sampling signal used to
acquire it.
Today’s serial-communication systems have opted to embed clock information in the data
stream rather than using an external trigger signal at the receiver. The clock must therefore
be recovered from the received bit stream itself. This function, known as Clock and Data
Recovery (CDR), is shown in the block diagram for a typical SERDES receiver (Figure 3). If,
however, the incoming signal has more than a certain amount of jitter or phase noise, the
recovered clock cannot stay accurately aligned with the data. Misalignment causes an
inaccurate placement of individual data points in time.
4. To minimize the bit error rate (BER) you must properly time this phase shift with the data
stream, and for that reason serial-communication standards now place a greater importance
on high-accuracy measurement of jitter. Jitter is generally classified as deterministic jitter
(Dj) or random jitter (Rj). Because each is created differently, they are characterized
separately.
Two Fundamental Components Of Jitter
Random jitter (Rj) represents timing noise with no discernable pattern. For the purpose of
modeling, it is assumed to have a Gaussian probability distribution (Figure 4). Usually due
to forces of nature, random jitter is statistical and unbounded. (It is characterized by its
standard deviation value, expressed as an rms quantity.) Thus, providing an Rj spec without
a sample size does not make much sense. Other than measuring the value of Rj in a system,
however, most designers do little else with this parameter. Finding the cause of Rj is a
difficult task, and beyond the scope of this article.
5. Deterministic jitter (Dj) is caused by events in the system, and appears as timing noise with
somewhat discernable patterns. It is usually repeatable, persistent, and predictable. In
addition, it is typically the result of faulty design in areas such as the circuit, the layout, and
the transmission line. It is typically non-Gaussian, as is power-supply noise due to a bad
reference plane.
Deterministic jitter is further classified into sub-components: periodic jitter (Pj in Figure 5),
data-dependent jitter (DDj, also known as inter-symbol interference, or ISI), duty-cycle-
distortion jitter (DCDj), and any other timing jitter that is uncorrelated and bounded to the
data. Pj can be caused by cross-talk (from other signals and from semiconductor switching
close to the serial-data signals), electromagnetic interference (EMI), and other unwanted
modulation. DCDj results from unbalanced transitions in the data (differences in rise and
fall times), and DDj is jitter correlated with bit sequences in the data stream (also affected
by the channel’s frequency response)[1].
6. Total Jitter (Tj)
As you might guess, total jitter is composed of random and deterministic
components(Figure 6). There are several techniques for estimating Tj. Some find the total
jitter by resolving it into Rj and Dj components, then adding them together using a
multiplier in front of the Rj component. Other methods find total jitter by extrapolating the
histogram of time interval error (TIE) measurements. Tj is usually a peak-to-peak value
expressed in pico-seconds or fractions of a unit interval (UI). For example, 0.2UI means
that jitter is 20% of the data eye.
7. To predict the overall performance of a system, you must understand the types of jitter and
their effects. Because jitter causes timing errors, it has become increasingly important to
characterize and qualify all jitter components in a system. Before that can be done, however,
you must determine the sources of jitter. As mentioned earlier, the two types (random and
deterministic) have different sources. A designer has little or no control over the sources of
Rj in an existing system of embedded circuit boards[1], but he can use good design practices
to greatly mitigate or even eliminate the sources of deterministic jitter. Each jitter
component has a specific cause, as shown in (Table 1)[1].
Proposed Link-Characterization Framework
The proposed link-characterization framework we will discuss helps to identify and measure
the sources of clock and data jitter. The technique hinges on the designer’s ability to
separate jitter sources, and to focus on the problem areas revealed by this testing
framework. Jitter testing generally requires the observation of a repeating test pattern on
the channel.
The data pattern to be used is important, because reflection and intersymbol interference
(ISI) are both data-dependent sources of noise. The test patterns used to collect the majority
of plots in this paper included a mixed-frequency repeating K28.5 sequence (also known as
8. the comma character: K28.5 = 00111110101100000101), and a pseudo-random bit sequence
(PRBS-23). PRBS patterns give a good spread of the different bit sequences that might be
observed in actual data traffic. Other compliance test patterns for jitter evaluation are
available, including the Jitter Test Pattern (JTPAT), Compliance Random Pattern (CRPAT),
and Compliance JTPAT (CJTPAT), to name a few.
The key to getting accurate measurements lies in selecting the right measurement
equipment for your application (oscilloscopes and probes, for instance). For step 1 of this
framework (and for the remaining steps as well), the signal is measured after it has
propagated through a channel of 50-Ω transmission line that also includes the cable,
connector, and FR-4 PCB. You should solder a differential, high-performance probe with
high bandwidth and low capacitive loading to the PCB trace as close as possible to the
receiver IC.
STEP I: Quantify Random And Deterministic Jitter (Rj And Dj)
The first step is to observe the signaling level. Then, you collect link measurements and
compare them to the standard. (Table 2 gives an example of measurements versus the XAUI
specification, which is measurement of the PHY’s input characteristics.) The SI engineer can
create a similar matrix for the standard against which his system is being tested.
An eye diagram is one of the most important measurement techniques used in assessing
high-speed signal integrity. It overlays waveforms from multiple unit intervals (UI) using
either the real clock or a reconstructed clock as the timing reference. Because the eye
diagram helps you to visualize amplitude behavior as well as the timing behavior of a
waveform, it represents one of the most useful presentations of jitter. Figure 7) shows an
eye diagram measurement taken from a XAUI channel.
9. Using timing-analysis software loaded on the scope (TDSJIT3 from Tektronix, for instance)
and with the scope set for “golden PLL,” the SI engineer can set the parameters shown
in Table 2 and capture an eye diagram of the channel traffic. Then, he can complete the
matrix shown in Table 2 for the particular standard being used. (Golden PLL is a method for
filtering out jitter on the scope trigger, thereby ensuring that any jitter represented in the
measured jitter amplitude and histograms is actually present on the linkC.)
STEP II: Amplitude Noise Or Voltage Error Histograms
This step measures amplitude noise, which can cause error in the design. We are looking to
see if the probability density functions (PDFs) for amplitude have a normal distribution for
both the “1” and “0” levels. (Figure 8 shows the PDFs for a XAUI link.) The random-
amplitude noise shown in blue in the histograms (circled in red) can be considered as
normal distributions. The SI engineer can also use this plot as a graphic aid in determining
10. whether other signaling issues are present, such as overshoot and undershoot. If amplitude
noise is an issue (if the amplitude histograms are bi-modal, for instance), then we likely
have a power-distribution problem on the board.
STEP III: Eye Diagram Versus “Far-End” Mask Analysis
In Step III, the SI engineer estimates jitter quality for the received signal over a long
sequence of data. Many jitter application packages include standard masks, whose
minimum-closure dimension allows you to rate the quality of the measured channel. By
comparing the eye diagram to the receive masks, you can view the amount of eye closure in
a given configuration. The eye should be clear of the masks (Figure 9).
11.
12. At this stage, the tester also analyzes the eye plot’s rising edges separately from the falling
edges. In the example of Figure 10, you can clearly observe that the rising and falling edges
are not aligned in the middle at the eye crossing point (the bi-modal histogram circled at
mid-top of the figure). This bi-modal histogram is an indication of the presence of cycle-to-
cycle or periodic jitter on the channel. The histogram could also represent DCD or ISI
jitters.
Designers often limit their testing to a measurement of total jitter and only view the
histogram, which represents the total jitter (Dj and Rj mixed together). To understand the
root cause of jitter and eliminate its contributing components, it’s essential to separate and
identify each component. Since the eye diagram is a general tool that gives insight only into
the amplitude and timing behavior of the signals, other means are needed to separate the
13. jitter components. In the next step, we separate total jitter into its components by analyzing
the jitter histogram and bathtub plots.
STEP IV: Separate Jitter Types And Components
Keeping jitter out of the system requires that you be able to separate the random and
deterministic jitter components. For that purpose, the technique described in this step helps
with debugging and design verification as well as characterization of the system links. We
now analyze some of the histograms collected in the previous sections.
Histogram Plot
The total jitter histogram is a good first look at the analysis of jitter. As mentioned in a
previous section, random jitter (Rj) is assumed to have a Gaussian (normal) distribution for
the purpose of modeling. That means that its probability density function is described by the
well known bell curve. The time interval error (TIE) histograms associated with our PRBS-
23 data are shown in Figure 11. Note that the total jitter histogram can also be multi-modal.
14. The histogram of Figure 11a is not necessarily okay, but that of Figure 11b definitely points
to some poor design issues. As shown in Figure 10, it is easy to see that a bi-modal
histogram has something to do with the rising and falling edges not being aligned in the
middle (some systemic problem is messing up the histogram and making it non-Gaussian).
A bi-modal histogram usually indicates significant amounts of deterministic jitter.
When both Dj and Rj components are present, the jitter histogram is generally broadened,
and no longer resembles a Gaussian distribution. In that case, the difference between the
left and right peak values represents Dj, and results from a crossing point that is a bit higher
than it should be. This condition can be associated with DCD jitter due to a cross-talking
signal with a given period. That’s why it is important that designers analyze the histograms
as complementary insights to eye diagrams.
Bathtub Plot
15. Like the histogram, the bathtub plot offers a powerful way to look at jitter and analyze its
timing. By plotting bit error rate as a function of sampling position within the bit interval,
the bathtub plot represents eye opening versus bit error rate (Figure 12). (Operation at an
expected maximum error rate of 10–12 has become a defacto requirement in many serial
standards.) As can be observed in the figure, deterministic jitter forms the almost flat
horizontal portion of the bathtub curve (gold region), while the slope portion (blue region)
is due to random jitter. You can also see that that the following equation applies:
Jitter Eye Opening + Total Jitter = 1UI.
The measurement of a jitter histogram, or bathtub curve, or both, is a primary step
informing the SI engineer of jitter in the system. Neither measurement, however, tells him
about the individual sources of the jitter components. In the next step, we attempt to
identify the root cause(s) of Dj by separating it into its components.
STEP V: Diagnose The Root Cause Of Jitter
We now analyze jitter in the frequency domain, which reveals Dj components (Pj, ISI, DCD,
etc.) as distinct single-frequency spurs (line spectra) that can easily be visualized to analyze
their sources. These frequency domain views can include the phase noise plot, the jitter
spectrum plots, or a Fast Fourier Transform (FFT) of the jitter trend.
16. Jitter Spectrum Of Data TIE Plot
Several techniques are available for measuring jitter on a single waveform. One such
technique is to examine the spectrum of the time interval error (TIE). TIE is the timing
deviations of digital-data transitions from their ideal (jitter-free) locations. In short, the TIE
measures how far each active edge of the clock varies from its ideal position. TIE is
important because it shows over time the cumulative effect that is produced by even a small
amount of jitter[2].
Going back to the serial link being characterized, Figure 13 shows a plot of the jitter
spectrum of the TIE taken on the link. In the figure, the spurs present a snapshot of the
channel at a specific point in time. The spurs have been numbered F1, F2, F3, and F4 for
reference purposes. The first spur is at F1 = 61.44 MHz (the fundamental frequency of the
recovered clock). The spurs F2 and F4 are integer multiples (harmonics) of F1. The spur that
does not seem to fit in (because there is no clock source on the board with this frequency) is
F3 at 153.18 MHz. F3 represents an intermodulation of two or more frequencies on the card.
It could also be produced when the high-speed signal crosses over a split in the
power/ground plane. When high-speed signals pass over a split reference plane, the
discontinuity in the return path for current can create emissions.
17. Spectral analysis
To reveal sources of jitter, the SI engineer must conduct a spectral analysis of the jitter
spectrum plot to get an idea of the modulation frequency of each jitter source. Frequency-
domain plots exhibit the unique frequency spurs. You can isolate certain deterministic jitter
components using the following methods:
Isolating Periodic Jitter (Pj)
On occasion, the serial data channel will show a nice looking histogram (a Gaussian
distribution), yet the spectrum of time interval error (TIE) on the same link shows some
spurs. That means a small Pj can be buried in the random jitter and not be visible on the
histogram of total jitter. It is therefore worthwhile to do the spectral analysis just so all
bases are covered, even when the jitter numbers have not gone out of spec.
In the spectrum plot analysis above, F3 was regarded as the result of an unwanted
modulation. It is this type of unwanted modulation (due to EMI or cross-talk, for instance)
that usually causes Pj. The signature of period jitter is that it repeats at a fixed frequency.
Such unwanted modulation can also be caused by cross-coupling, such as switching noise
from the power-supply module coupling into the data or system clock.
Isolating Duty Cycle Distortion (DCD)
DCD points to differences in the rise and fall times of the digital transitions, and to
variations in switching thresholds for the devices previously mentioned. DCD is caused by
voltage offsets between differential inputs, and by differences in the system rise and fall
times. The rise and fall edges in Figure 9, for example, are not aligned in the middle. An SI
engineer can attempt to isolate DCD by stimulating the system with a high-frequency
pattern such D21.5 (1010101010…). That pattern is effective in exposing DCD while
eliminating ISI.
Isolating Inter Symbol Interference (ISI)
A common source of data-dependent jitter (DDj) is the frequency response of the signal
path through which the serial data is transmitted. ISI is a type of data-dependent jitter. It is
created in the channel lineup that includes the cable and connectors, and is affected by
losses in the FR4 PCB material. Because ISI is usually the result of a bandwidth limitation in
either the transmitter or the signal path, limited rise and fall times in the signals can
produce varying amplitudes for the data bits[2]. Another primary source of DDj is
18. impedance mismatch in the channel lineup, due to an improper termination of the bus.
Reflections caused by a transmission line with mismatched termination impedance can
cause delays and/or attenuation of the transmitted signals.
STEP VI: Optimizing Tx Pre-Emphasis And Rx Equalization
It’s well established that the amount of attenuation caused by lossy FR4 traces on a PCB
depends on the signaling speed and the length of the transmission medium. In short, FR4
losses are more severe at the higher switching frequencies. Pre-emphasis and equalization
can mitigate the effects of signal attenuation and degradation, thereby restoring the original
signal. This link-optimization step not only applies to designs with PHY devices that support
transmitter pre-emphasis and receiver equalization, but also to discrete ICs for pre-
emphasis and equalization, which can be used to compensate for the transmission losses
caused by FR4 material. This last step of the framework applies to designs that include
provision for tuning the pre-emphasis and equalization levels of SERDES/PHY devices. We
therefore assume the system in question includes such provisions.
Optimal Pre-Emphasis
Pre-emphasis is a signal-improvement technique that opens the eye pattern at the far end of
a cable (at the receiver). In general, pre-emphasis increases the transmitted signal quality by
increasing the magnitude of some frequencies with respect to the magnitude of other
(usually lower) frequencies. The key is to find the optimal pre-emphasis setting for the
design.
For SERDES and PHY devices that support different levels of pre-emphasis, the SI engineer
can step through the levels and select the one with the best eye, or the one that achieves a
BER of 10–12or better. Also available are pre-emphasis driver ICs (such as the MAX3982
from Maxim) that can be used to optimize performance by manually tuning the transmitter
with respect to eye-opening and ISI jitter at the receiver.
One slight advantage of using a discrete pre-emphasis IC versus one that is embedded in a
SERDES/PHY device is that the tester can capture an eye diagram at the receiver input,
with a scope, and quickly see an improvement in the signal quality. The wider the eye, the
better the quality. The SI engineer should therefore look for the best eye opening using the
least amount of pre-emphasis. The rule is: don’t over-preemphasize. An optimal setting
should provide some improvements in the channel’s overall jitter performance.
19. Optimal Equalization
Besides adding pre-emphasis, you can also minimize the effects of ISI by optimizing the
equalization setting at the receiver. The purpose of the equalizer is to remove and/or
overcome the effects of high-frequency attenuation introduced on the waveform while
traveling on the PCB and cable. The receive device’s equalizer compensates the received
signal for dielectric and skin losses in the PCB material, as well as for high-frequency loss in
the cable.
In the practical and experimental sense, the effects of received equalization are difficult to
evaluate when that function is embedded in an IC of the SERDES/PHY device. External
receiver-equalizer ICs (such as the MAX3784) can provide a way to quickly observe the
results of receiver equalization on the scope (as opposed to BER testing for a
SERDES).Figure 14shows the MAX3784 equalizer input eye diagram before and after
equalization, at a signaling rate of 5 Gbps. These measurements were made on a 40-inch, 6-
mil trace (stripline) on FR4 PCB material.
Link performance
While pre-emphasis at the transmitter helps to mitigate interference caused by adjacent
symbols in the data, equalization at the receiver can also help to achieve a similar result, as
shown in Figure 14. Pre-emphasis and equalization together are the main techniques in use
today for reducing or overcoming transmission losses in serial-transmission mediums.
20. An important question is: how much pre-emphasis and/or equalization is enough? That
depends on the application and the channel line-up. Blindly setting the system for too much
pre-emphasis or equalization can have negative effects on the system. The SI engineer must
take signal-quality measurements to determine the proper amount of pre-emphasis and
equalization for a given application. Maxim has a large portfolio of pre-emphasis and
equalizer ICs for circuit board and cable applications, covering the range from 1 Gbps
(MAX3803) to 12.5 Gbps (MAX3804). For more information, refer to Figure 15 and
to www.maxim-ic.com/equalizerSolutions.
21.
22. If you design a high-speed digital system today, chances are that you will have a jitter spec
or a jitter budget to meet. Understanding jitter and its causes allows you to create high-
performance systems. The accurate separations of total jitter into random and deterministic
jitter, and deterministic jitter into its sub-components (Pj, DCD, ISI), is not only imperative
for compliance with the serial standard, but also important in providing diagnostic
information for improving the design.
Designers must ensure that their designs work for reasons of competitive advantage, but
they must also know the point at which their design stops working. By identifying jitter and
its sources, the link-characterization framework proposed in this paper should help to
improve system performance (Figure 16).
23. References:
[1] Jitter fundamentals, “Enhance Speed, Throughput and Accuracy with One Powerful
Instrument,” Wavecrest: A Technologies Company, Eden Prairie, Minnesota, available
atwww.wavecrest.com.
[2] A Guide to Understanding and Characterizing Timing Jitter, Tektronix Enabling
Innovation Primer, available at www.tektronix.com/jitter.
Characterizing High-Speed Serial Communications Links
Requires Some Analog Savvy