Toshiba Asic & Foundry ELDEC Flyer


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Toshiba ASIC & Foundry - European LSI Design and Engineering Centre

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Toshiba Asic & Foundry ELDEC Flyer

  2. 2. ELDEC – LOCAL EXPERTISE DESIGN METHODOLOGY AND FOR THE EUROPEAN MARKET KNOWLEDGE MANAGEMENT Toshiba's European LSI Design and Engineering Centre (ELDEC) Knowledge Management is the key to ELDEC’s success in was founded as a strong and sustainable contributor to the supporting both customer and in-house developments. Through ongoing semiconductor operations of Toshiba Electronics Europe Knowledge Management processes and investment in specific GmbH (TEE). ELDEC’s mission is to meet the needs of European local competencies - including sophisticated design review customers and proactively address market requirements through stages - ELDEC delivers ‘right first time’ silicon, minimising the development and delivery of innovative, high-quality, silicon time-to-market and reducing development time and cost. products with minimum time-to-market. The ELDEC Design Methodology Development team drives ELDEC provides TEE’s ASIC & Foundry customers with integrated, continuous design platform innovation for deep sub-micron custom, system-on-chip (SoC) solutions; develops Toshiba’s own designs. The team also defines and supports the latest technology application specific standard products (ASSPs) and associated design tools and methodologies. ELDEC’s focus on Knowledge embedded software; and provides application support for the Management also helps Toshiba and its customers to develop an company’s comprehensive family of microcontrollers and ASSPs. early understanding of market opportunities and future technologies. Operating from TEE’s European headquarters in Düsseldorf, Germany, ELDEC employs over 100 highly skilled local engineers. These engineers are involved in all aspects of LSI development including hardware and software design, creation of IP building blocks and SoC implementation. ELDEC’s engineers also create SoC-based reference systems and specify and produce design and software tools. ELDEC’s competencies cover high-density, complex ASICs, ASSPs and systems. Target applications include telecommunications, networking, multimedia and automotive. SIL ON IMP ICO TI T LE N M & T DA S DE TAT E EN LI SIG ION VA N& SYS High quality technical solutions and support encompass pre-sales TE and design stages, prototyping and final manufacture. Full E M AR D ES W integration with Toshiba’s global research and development IG FT N SO organisations provides access to technical expertise at other Toshiba engineering centres including those in Japan, Taiwan and the United States. Initiatives designed to optimise solutions ELDEC is committed to delivering high-quality solutions and at a local level include strong European relationships with leading services to its customers on time and within budget. To continually EDA vendors. improve project execution ELDEC employs 6 Sigma methodologies for all core activities. By establishing specific competencies, producing and exchanging hard and soft IP and sharing its know-how, ELDEC makes a significant contribution to Toshiba's worldwide design and engineering activities.
  3. 3. IMPLEMENTATION AND DESIGN SERVICES (IDS) From RTL-to-GDS and on into final packaging and tape-out ELDEC’s Implementation and Design Services (IDS) cover every aspect of chip design, implementation and production. ELDEC can support integrated ICs with gate counts ranging from 50,000 to 15 million based on Toshiba’s leading edge advanced CMOS processes at 130nm, 90nm, 65nm and 40nm process nodes. Services covered by ELDEC IDS include: Consultancy for all RTL design issues TOSHIBA’S IP LINEUP Synthesis Toshiba’s leading edge one pass design flow delivers minimum Chip layout turn-around-time (TAT) implementation with the lowest possible Integration of mixed-signal IP risk through early quality checks, rapid prototyping and single-pass Complex memory integration final implementation. Low power design Design for test (DFT) DESIGN & Test pattern generation HARDWARE DESIGN IMPLEMENTATION PIN-LIST At-speed tests PLANNING & PROTOTYPING > 4 WEEKS RT-LEVEL PIN-OUT DESIGN & VERIFICATION Special I/O tests including: DDR2/3 STRUCTUAL NETLIST & DFT: S-ATA PROTOTYPE CONSTRAINTS MEMORYBIST & SCAN Static timing analysis (STA) SYNTHESIS Yield optimisation DFT: JTAG PROTOTYPE LAYOUT Package selection and design including: Cost, performance and thermal considerations BACK Multi-chip module (MCM) and System-in-package PROTOTYPE ANNOTATION TIMING OPTIMISATION (SiP) solutions STA I/O assignment Substrate design support including signal integrity design Support for quality audit (QA) procedures NETLIST & FINAL CONSTR. DFT: SYNTHESIS DFT: JTAG MEMORYBIST & SCAN FINAL IMPLEMENTATION 1-2 WEEKS All aspects of ELDEC support in Europe are coordinated via local TIMING project management teams, backed by links to both local and OPTIMISATION global experts. FUNC. RTL FINAL LAYOUT MOD. STATIC Project management services continue through into successful TIMING CROSSTALK- & SI-FIXES ANALYSIS mass production and ensure reliable schedule planning while GATE- (STA) BACK- TIMING FIXES providing the benefit of a single point of contact for all technical LEVEL ANNOTATION SIM. FORMAL VERIFICATION (GL) queries, advice and guidance. Project managers provide customers with high levels of visibility MASK of project status through ‘live’ tracking documentation. This FINAL VERIFICATION APPROVAL (2ND SIGN-OFF) TAPE-OUT includes status updates, risk management procedures and action identification and ownership. For maximum customer benefit Toshiba aims to become involved as early as possible in the planning and prototyping phase. Toshiba’s ELDEC specialists can provide early design and concept quality checks in areas such as pin-out, clock architecture and key design constraints. Several prototyping iterations may occur during this phase to ensure that the final implementation can be performed in a single pass.
  4. 4. Benefits include access to: Advanced 130nm, 90nm, 65nm and 40nm CMOS processes A comprehensive range of mixed-signal and analogue IP Digital IP including processors and cores Local project management Resources for early identification of IP and other technologies MIXED-SIGNAL IP for future applications and markets Skilled engineers with wide-ranging experience in all areas of As advanced CMOS processes enable ever more sophisticated ASIC design, implementation and system architecture definition. SoC designs, the demand for linking core digital processing functionality with the real ‘analogue’ world becomes more Unlike third party design houses, Toshiba’s Integrated Device important. As a result, mixed-signal and analogue Intellectual Manufacturer (IDM) model allows the company to provide total SoC Property (IP) building blocks have become a critical factor in competence. Customers can deal with a single organization from efficient SoC and ASSP development. initial IP sourcing to design, through testing and on into final manufacture. ELDEC’s experience and expertise has supported the seamless integration of complex analogue and mixed-signal IP cores into a IP DEVELOPMENT PRODUCT large number of SoC designs. As well as local expertise, ELDEC AND SUPPORT SOC DEVELOPMENT can draw on the considerable resources and mixed-signal IP COMPETENCE expertise at other Toshiba research and development centres around the world. PROCESS IMPLEMENTATION QUALIFICATION TOSHIBA AND LIBRARY WAFER Through ELDEC Toshiba also supports customers looking to FAB develop their own mixed-signal solutions. ELDEC can provide a Process Design Kit (PDK) for the required technology node MANUFACTURING as well as evaluation, verification and qualification support. This TECHNOLOGY DEVELOPMENT • WAFER ASSEMBLY • TEST FEEDBACK ensures the IP meets the same strict quality and stability criteria as the company’s own IP. As an IDM, Toshiba has intimate involvement with the underlying THIRD PARTY IP IN-HOUSE IP process technology and rapid access to production feedback. This ensures that designs can be optimized and customized with final DESIGN DESIGN production in mind from the very beginning. What’s more, all of the hard macro IP cores developed by Toshiba’s engineering teams are VERIFICATION guaranteed to be fully compatible and optimized for the company’s (SIMULATION, RULE-CHECKING...) VERIFICATION (SIMULATION, advanced SoC processes. This guarantee also applies to third party ACCEPTANCE VERIFICATION RULE-CHECKING...) architecture-based IPs provided through the Toshiba channel. Such IPs are subject to exactly the same rigorous qualification EVALUATION, and verification procedures. EVALUATION, QUALIFICATION (TESTCHIP ON TOSHIBA (TESTCHIP ON TOSHIBA TECHNOLOGY) TECHNOLOGY) For the customer, the IDM model also eliminates the blurring of the boundaries of responsibility. Toshiba’s responsibility encompasses VALIDATION VALIDATION everything from IP to final production and yield optimization. This (REAL-MACHINE (REAL-MACHINE gives customers the peace of mind that they are working with a ENVIRONMENT) ENVIRONMENT) company that shares their objective of delivering successful volume silicon in the shortest possible TAT. PERFORMED BY TOSHIBA PERFORMED BY IP PROVIDER SOC HANDOVER MODELS Whether the IP is developed by ELDEC or starts life with a To speed up and simplify the implementation of SoCs based customer or third party design house it is subjected to the same on the company’s advanced CMOS processes; Toshiba offers rigorous design verification methodologies. This includes full a variety of development handover models including: testing of the IP in target applications and validation of the interoperability and system level quality of interface system IP using application boards. ASIC MODEL RTL handover with synthesis, place-and-route, and verification by Toshiba or gate-level handover with synthesis by customer SUPPORT FOR CUSTOMER SOCS and layout implementation by Toshiba Toshiba ELDEC support for customer SoC development in SEAMLESS “HYBRID” MODELS Europe is provided via Toshiba Electronics Europe’s ASIC & Mixed-signal IP/block development by customer based on Foundry Business Unit. Working with ELDEC this business can PDK, and chip-level integration by Toshiba (RTL handover evaluate and develop product requests, perform technical and or gate-level handover) commercial feasibility studies, define system architectures and provide access to IP. FULL COT (CUSTOMER OWN TOOLING) MODEL Physical data handover (GDSII) by customer. In each handover model ELDEC engineers are available to provide full technical support, advice and guidance relating to the integration-, QA- and testing of the FPD IP.
  5. 5. SUPPORT FOR ASSPS CAMERA DISPLAY HDMI DISPLAY ELDEC creates integrated, high-performance ASSPs for BUFFER automotive, telecommunications, multimedia and industrial MIPI DISPLAY BUFFER applications. Successful application-specific designs include BRIDGE SoCs for vehicle instrument clusters, ABS subsystems and BRIDGE embedded mobile peripherals for cellular handsets. HUB TV TOSHIBA ASSP SCOPE OF WORK BASEBAND (APPLICATION) ARCHITECTURE MARKETING TECHNICAL Global Technical Market Research PROCESSOR TV OUTPUT BUFFER Product Concept Definition LED KEYBOARD Promotion activities / Sales support 1 2 3 4 5 6 Technical Customer Interface 7 8 9 SYSTEM & * 0 # System design and simulation (HW/SW) I/O EXPANDER Design for test MIPI® word marks and logos are service VLSI design, implementation and test marks owned by MIPI Alliance, Inc. VALIDATION IMPLEMENTATION IP design (digital and mixed signal) In the automotive arena Quality Management ELDEC develops ASSPs that (KM, KCR, QS9000, TS16949) support CAN, MediaLB™, Standardization (contributing and consuming) APIX® and FlexRay™ solutions. - MIPI, MPEG, OpenGL, OpenVG, ARM) Automotive expertise includes development of graphic PCB design (test & reference) subsystems deployed in VLSI and SW validation instrument cluster and infotainment applications. Conformancy and interoperability testing PRODUCT SUPPORT Device characterization ELDEC CPU core integration and CPU sub-system development incorporates a wide variety of embedded ARM cores, embedded Application support HW & SW MIPS cores and Toshiba’s own Media embedded Processor (MeP) technology. ELDEC support for ASSP implementation starts with market research and product planning. System architects and project ELDEC’s embedded software experience includes MPEG-2 and managers then create system specifications and project plans MPEG4 firmware, driver software, graphic controller algorithms, encompassing all aspects of LSI product development and graphic accelerators, image recognition firmware and middleware. support, including: Embedded RTOS expertise covers Embedded Linux, Khronos System design and simulation API and NoTA. ELDEC teams also develop software for home Circuit design appliances, motor control and vehicle information systems. Concept and design for test Silicon implementation Through ELDEC Toshiba provides turnkey reference designs, Power and EMC optimization FPGA prototyping, evaluation boards, documentation and other Package planning services to speed the evaluation and implementation of Toshiba Verification and validation ASSPs and microcontrollers in customer applications. Device characterization Datasheet creation ELDEC also provides technical and application support for Toshiba’s Software support comprehensive family of standard microcontrollers and micro- Mass production support processors, including the latest devices based on ARM® cores. Continuous quality and reliability control In support of its ASSP Embedded hardware expertise covers high-speed interfaces up development programs to 10Gbps and industry- and de-facto-standard interfaces such Toshiba contributes to and as MIPI®, HDMI, PCI, USB, and serial ATA. participates in standards bodies and has a number For mobile telecoms applications ELDEC develops mobile of relevant quality engineering peripheral SoCs for camera, display and audio-video subsystems. certifications. These include These SoCs enrich the functionality of cellular phone platforms TS16949 for automotive project management and development, and support enhanced, ‘ready-to-go’ embedded connectivity. SIL-1 for safety critical systems such as ABS, and conformance and interoperability approvals for communication standards such as DVB, Bluetooth and MIPI.
  6. 6. MANUFACTURING COMPETENCIES, SUPPLY CHAIN MANAGEMENT AND LOGISTIC SUPPORT Toshiba handles its own process development, and has its own, fully controlled wafer fabs, packaging and test facilities. SoCs and ASSPs created by ELDEC are manufactured at Toshiba’s 300mm wafer-fabrication facilities in Oiita and Nagasaki. The company continues to invest in technology and fab capacity to ensure reliable support of customer requirements and the needs of its own ASSP programme. Toshiba is able to commercialize leading-edge CMOS processes for advanced ICs one to two years ahead of the industry, to the direct benefit of our 300mm manufacturing customers. By leading the industry in producing high-performance system-level ICs in 90nm since 2003, plus early production of 65nm in 2006—with development of 40 and 28nm process technologies underway— Toshiba is able to stay ahead of the yield curve and is continually solving DFM complexities to enhance performance, streamline time-to-revenue and reduce IC cost. Oiita Fab Nagasaki Fab GERMANY FRANCE ITALY TOSHIBA ELECTRONICS EUROPE GMBH TOSHIBA ELECTRONICS EUROPE GMBH, TOSHIBA ELECTRONICS EUROPE GMBH, CENTRAL EUROPEAN SALES FRANCE BRANCH ITALY BRANCH Hansaallee 181, 40549 Düsseldorf Les Jardins du Golf, 6 rue de Rome, Centro Direzionale Colleoni, Palazzo Perseo Tel.: +49 (0211) 5296 0 F-93561 Rosny-Sous-Bois, Cédex, Paris Ingresso 3, Via Paracelso 14, I-20041 Fax.: +49 (0211) 5296 400 Tel.: +33 (1) 48 12 48 12 Agrate Brianza, Milan Fax.: +33 (1) 48 94 51 15 Tel.: +39 (039) 68701 Fax.: +39 (039) 6870205 UK SPAIN SWEDEN TOSHIBA ELECTRONICS EUROPE GMBH, TOSHIBA ELECTRONICS EUROPE GMBH, TOSHIBA ELECTRONICS EUROPE GMBH, UK BRANCH SPAIN BRANCH SWEDEN BRANCH Delta House, The Crescent, Parque Empresarial, San Fernando, Edificio Gustavslundsvägen 18, 5th Floor, Southwood Business Park, Europa, 1ª Planta, E-28831 Madrid S-167 15 Bromma Farnborough, Hampshire GU14 ONL Tel.: +34 (91) 660 6798 Tel.: +46 (08) 704 0900 Tel: +44 (0870) 0602370 Fax.: +34 (91) 660 6799 Fax.: +46 (08) 80 8459 Fax: +44 (01252) 530250 TOSHIBA is continually working to improve the quality and reliability of its products. instruments, transportation instruments, traffic signal instruments, combustion control Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent instruments, medical instruments, all types of safety devices, etc. Unintended Usage of Toshiba electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when products listed in this document shall be made at the customer's own risk. The products utilising TOSHIBA products, to comply with the standards of safety in making a safe design for described in this document may include products subject to the foreign exchange and foreign the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA trade laws. products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as The information contained in this document is presented only as a guide for the applications of set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the our products. No responsibility is assumed by TOSHIBA for any infringements of patents precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or or other rights of the third parties which may result from its use. No license is granted by "TOSHIBA Semiconductor Reliability Handbook" etc.. implication or otherwise under any patent or patent rights of TOSHIBA or others. The Toshiba products listed on this document are intended for usage in general electronics Copyright and published by Toshiba Electronics Europe GmbH; Hansaallee 181- 40549 applications (computer, personal equipment, office equipment, measuring equipment, Düsseldorf Handelsregister Düsseldorf HRB 22487; Geschäftsführer: Ryoichi Shikama; industrial robotics, domestic appliances, etc.). These Toshiba products are neither intended nor Amtgericht Düsseldorf warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Products or company names mentioned herein are Trademarks of their respective owners. Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship The information contained herein is subject to change without notice.