Scheduling and Allocation Algorithm for an Elliptic Filterijait
A new evolutionary algorithm for scheduling and allocation algorithm is developed for an elliptic filter. The elliptic filter is scheduled and allocated in the proposed work which is then compared with the different scheduling algorithms like As Soon As Possible algorithm, As Late As Possible algorithm, Mobility Based Shift algorithm, FDLS, FDS and MOGS. In this paper execution time and resource utilization is calculated using different scheduling algorithm for an Elliptic Filter and reported that proposed Scheduling and Allocation increases the speed of operation by reducing the control step. The proposed work to analyse the magnitude, phase and noise responses for different scheduling algorithm in an elliptic filter.
Scheduling and Allocation Algorithm for an Elliptic Filterijait
A new evolutionary algorithm for scheduling and allocation algorithm is developed for an elliptic filter. The elliptic filter is scheduled and allocated in the proposed work which is then compared with the different scheduling algorithms like As Soon As Possible algorithm, As Late As Possible algorithm, Mobility Based Shift algorithm, FDLS, FDS and MOGS. In this paper execution time and resource utilization is calculated using different scheduling algorithm for an Elliptic Filter and reported that proposed Scheduling and Allocation increases the speed of operation by reducing the control step. The proposed work to analyse the magnitude, phase and noise responses for different scheduling algorithm in an elliptic filter.
The aim of the query optimizer is not only to provide the SQL engine execution plans that describe how to process data but also, and more importantly, to provide efficient execution plans. Even though this central component of Oracle Database is enhanced with every new release, there are always cases where it generates suboptimal execution plans. The aim of this presentation is to describe and demonstrate how, with Adaptive Query Optimization, which is a set of features available as of Oracle Database 12c, the query optimizer is able to generate less suboptimal execution plans.
Comparative Study on the Performance of A Coherency-based Simple Dynamic Equi...IJAPEJOURNAL
Earlier, a simple dynamic equivalent for a power system external area containing a group of coherent generators was proposed in the literature. This equivalent is based on a new concept of decomposition of generators and a two-level generator aggregation. With the knowledge of only the passive network model of the external area and the total inertia constant of all the generators in this area, the parameters of this equivalent are determinable from a set of measurement data taken solely at a set of boundary buses which separates this area from the rest of the system. The proposed equivalent, therefore, does not require any measurement data at the external area generators. This is an important feature of this equivalent. In this paper, the results of a comparative study on the performance of this dynamic equivalent aggregation with the new inertial aggregation in terms of accuracy are presented. The three test systems that were considered in this comparative investigation are the New England 39-bus 10-generator system, the IEEE 162-bus 17-generator system and the IEEE 145-bus 50-generator system.
A multi objective hybrid aco-pso optimization algorithm for virtual machine p...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Prepare for the Worst: Reliable Data Protection with Oracle RMAN and Oracle D...Szymon Skorupinski
Oracle OpenWorld 2012 presentation
With tight schedules, increasing data volumes in an ever-growing number of databases, and the ever-present need for performance tuning and responding to user requests, a DBA’s life is never easy. How, then, to prepare for your primary responsibility: to be able to restore a database in the event of failure, no matter how catastrophic? This presentation shows how CERN prepares for such events with a centrally managed backup system and automated and regular test recovery—all thanks to standby databases and a dedicated NAS storage infrastructure, with minimal impact on production systems.
Even though 12.1.0.2 is "only" a patch set, it introduces a number of very interesting performance features. In-Memory Column Store is the most well known in this area. But, be aware, a number of additional features that, for example, helps optimizing the physical storage and the caching of data are also available. The aim of this session is to explain and demonstrate how these new features work.
Comparative study to realize an automatic speaker recognition system IJECEIAES
In this research, we present an automatic speaker recognition system based on adaptive orthogonal transformations. To obtain the informative features with a minimum dimension from the input signals, we created an adaptive operator, which helped to identify the speaker’s voice in a fast and efficient manner. We test the efficiency and the performance of our method by comparing it with another approach, mel-frequency cepstral coefficients (MFCCs), which is widely used by researchers as their feature extraction method. The experimental results show the importance of creating the adaptive operator, which gives added value to the proposed approach. The performance of the system achieved 96.8% accuracy using Fourier transform as a compression method and 98.1% using Correlation as a compression method.
Dynamic task scheduling on multicore automotive ec usVLSICS Design
Automobile manufacturers are controlled by stringent govt. regulations for safety and fuel emissions and
motivated towards adding more advanced features and sophisticated applications to the existing electronic
system. Ever increasing customer’s demands for high level of comfort also necessitate providing even more
sophistication in vehicle electronics system. All these, directly make the vehicle software system more
complex and computationally more intensive. In turn, this demands very high computational capability of
the microprocessor used in electronic control unit (ECU). In this regard, multicore processors have
already been implemented in some of the task rigorous ECUs like, power train, image processing and
infotainment. To achieve greater performance from these multicore processors, parallelized ECU software
needs to be efficiently scheduled by the underlaying operating system for execution to utilize all the
computational cores to the maximum extent possible and meet the real time constraint. In this paper, we
propose a dynamic task scheduler for multicore engine control ECU that provides maximum CPU
utilization, minimized preemption overhead, minimum average waiting time and all the tasks meet their
real time deadlines while compared to the static priority scheduling suggested by Automotive Open Systems
Architecture (AUTOSAR).
Windows server power_efficiency___robben_and_worthington__finalBruce Worthington
Computer Measurement Group Journal, Spring 2009.
Windows Server power efficiency has improved from release to release over the past decade. This paper presents the methodology and data used to validate the existing Windows Server power management algorithms, covers server-class processor and component power measurements, and discusses some Windows’ power measurement tools and future power optimizations.
The aim of the query optimizer is not only to provide the SQL engine execution plans that describe how to process data but also, and more importantly, to provide efficient execution plans. Even though this central component of Oracle Database is enhanced with every new release, there are always cases where it generates suboptimal execution plans. The aim of this presentation is to describe and demonstrate how, with Adaptive Query Optimization, which is a set of features available as of Oracle Database 12c, the query optimizer is able to generate less suboptimal execution plans.
Comparative Study on the Performance of A Coherency-based Simple Dynamic Equi...IJAPEJOURNAL
Earlier, a simple dynamic equivalent for a power system external area containing a group of coherent generators was proposed in the literature. This equivalent is based on a new concept of decomposition of generators and a two-level generator aggregation. With the knowledge of only the passive network model of the external area and the total inertia constant of all the generators in this area, the parameters of this equivalent are determinable from a set of measurement data taken solely at a set of boundary buses which separates this area from the rest of the system. The proposed equivalent, therefore, does not require any measurement data at the external area generators. This is an important feature of this equivalent. In this paper, the results of a comparative study on the performance of this dynamic equivalent aggregation with the new inertial aggregation in terms of accuracy are presented. The three test systems that were considered in this comparative investigation are the New England 39-bus 10-generator system, the IEEE 162-bus 17-generator system and the IEEE 145-bus 50-generator system.
A multi objective hybrid aco-pso optimization algorithm for virtual machine p...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Prepare for the Worst: Reliable Data Protection with Oracle RMAN and Oracle D...Szymon Skorupinski
Oracle OpenWorld 2012 presentation
With tight schedules, increasing data volumes in an ever-growing number of databases, and the ever-present need for performance tuning and responding to user requests, a DBA’s life is never easy. How, then, to prepare for your primary responsibility: to be able to restore a database in the event of failure, no matter how catastrophic? This presentation shows how CERN prepares for such events with a centrally managed backup system and automated and regular test recovery—all thanks to standby databases and a dedicated NAS storage infrastructure, with minimal impact on production systems.
Even though 12.1.0.2 is "only" a patch set, it introduces a number of very interesting performance features. In-Memory Column Store is the most well known in this area. But, be aware, a number of additional features that, for example, helps optimizing the physical storage and the caching of data are also available. The aim of this session is to explain and demonstrate how these new features work.
Comparative study to realize an automatic speaker recognition system IJECEIAES
In this research, we present an automatic speaker recognition system based on adaptive orthogonal transformations. To obtain the informative features with a minimum dimension from the input signals, we created an adaptive operator, which helped to identify the speaker’s voice in a fast and efficient manner. We test the efficiency and the performance of our method by comparing it with another approach, mel-frequency cepstral coefficients (MFCCs), which is widely used by researchers as their feature extraction method. The experimental results show the importance of creating the adaptive operator, which gives added value to the proposed approach. The performance of the system achieved 96.8% accuracy using Fourier transform as a compression method and 98.1% using Correlation as a compression method.
Dynamic task scheduling on multicore automotive ec usVLSICS Design
Automobile manufacturers are controlled by stringent govt. regulations for safety and fuel emissions and
motivated towards adding more advanced features and sophisticated applications to the existing electronic
system. Ever increasing customer’s demands for high level of comfort also necessitate providing even more
sophistication in vehicle electronics system. All these, directly make the vehicle software system more
complex and computationally more intensive. In turn, this demands very high computational capability of
the microprocessor used in electronic control unit (ECU). In this regard, multicore processors have
already been implemented in some of the task rigorous ECUs like, power train, image processing and
infotainment. To achieve greater performance from these multicore processors, parallelized ECU software
needs to be efficiently scheduled by the underlaying operating system for execution to utilize all the
computational cores to the maximum extent possible and meet the real time constraint. In this paper, we
propose a dynamic task scheduler for multicore engine control ECU that provides maximum CPU
utilization, minimized preemption overhead, minimum average waiting time and all the tasks meet their
real time deadlines while compared to the static priority scheduling suggested by Automotive Open Systems
Architecture (AUTOSAR).
Windows server power_efficiency___robben_and_worthington__finalBruce Worthington
Computer Measurement Group Journal, Spring 2009.
Windows Server power efficiency has improved from release to release over the past decade. This paper presents the methodology and data used to validate the existing Windows Server power management algorithms, covers server-class processor and component power measurements, and discusses some Windows’ power measurement tools and future power optimizations.
Haushaltsauflösung sowie wohnungsauflösung nrwNRW Schrott
Ob Haushaltsauflösung oder Wohnungsauflösung bei uns sind sie als Privatperson aber auch als Gewerbetreibende genau richtig. Haushaltsauflösung und Wohnungsauflösung nach einen Pauschalfestpreis.
CS 301 Computer ArchitectureStudent # 1 EID 09Kingdom of .docxfaithxdunce63732
CS 301 Computer Architecture
Student # 1
E
ID: 09
Kingdom of Saudi Arabia Royal Commission at Yanbu Yanbu University College Yanbu Al-Sinaiyah
Student # 2
H
ID: 09
Kingdom of Saudi Arabia Royal Commission at Yanbu Yanbu University College Yanbu Al-Sinaiyah
1
1. Introduction
High-performance processor design has recently taken two distinct approaches. One approach is to increase the execution rate by increasing the clock frequency of the processor or by reducing the execution latency of the operations. While this approach is important, much of its performance gain comes as a consequence of circuit and layout improvements and is beyond the scope of this research. The other approach is to directly exploit the instruction-level parallelism (ILP) in the program and to issue and execute multiple operations concurrently. This approach requires both compiler and microarchitecture support.
Traditional processor designs that issue and execute at most one operation per cycle are often called scalar designs. Static and dynamic scheduling techniques have been used to achieve better-than scalar performance by issuing and executing more than one operation per cycle. While Johnson[7] defines a superscalar processor as a design that achieves better-than scalar performance, popular usage of this term refers exclusively to those processors that use dynamic scheduling techniques. For clarity, we use instruction-level parallel processors to refer to the general class of processors that execute more than one operation per cycle of the computer both at the personal level, or the level of a small network of computers to do not require more of these types.
The primary static scheduling technique uses the compiler to determine sets of operations that have their source operands ready and have no dependencies within the set. These operations can then be scheduled within the same instruction subject only to hardware resource limits. Since each of the operations in an instruction is guaranteed by the compiler to be independent, the hardware is able to is- sue and execute these operations directly with no dynamic analysis. These multi-operation instructions are very long in comparison with traditional single-operation instructions and processors using .
Multi-cores have become ubiquitous both in the general-purpose computing and the
embedded domain. The current technology trends show that the number of on-chip cores is
rapidly increasing, while their complexity is decreasing due to power and thermal constraints.
Increasing number of simple cores enable parallel applications benefit from abundant thread-level parallelism (TLP), while sequential fragments suffer from poor exploitation of instruction-level parallelism (ILP). Recent research has proposed adaptive multi-core architectures that are
capable of coalescing simple physical cores to create more complex virtual cores so as to
accelerate sequential code. Such adaptive architectures can seamlessly exploit both ILP and TLP.
The goal of this paper is to quantitatively characterize the performance potential of adaptive
multi-core architectures. Previous research have primarily focused on only sequential
Workload on adaptive multi-cores. We address a more realistic scenario where parallel and
sequential applications co-exist on an adaptive multi-core platform. Scheduling tasks on adaptive
architectures reveal challenging resource allocation problems for the existing schedulers. We
construct offline and online schedulers that intelligently reconfigure and allocate the cores to the
applications so as to minimize the overall makespan under the constraints of a realistic adaptive
multi-core architecture. Experimental results reveal that adaptive multi-core architectures can
substantially decrease the makespan compared to both static symmetric and asymmetric multi-core architectures.
A methodology for full system power modeling in heterogeneous data centersRaimon Bosch
The need for energy-awareness in current data centers has encouraged the use of power modeling to estimate their power consumption. However, existing models present noticeable limitations, which make them application-dependent, platform-dependent, inaccurate, or computationally complex. In this paper, we propose a platform-and application-agnostic methodology for full-system power modeling in heterogeneous data centers that overcomes those limitations. It derives a single model per platform, which works with high accuracy for heterogeneous applications with different patterns of resource usage and energy consumption, by systematically selecting a minimum set of resource usage indicators and extracting complex relations among them that capture the impact on energy consumption of all the resources in the system. We demonstrate our methodology by generating power models for heterogeneous platforms with very different power consumption profiles. Our validation experiments with real Cloud applications show that such models provide high accuracy (around 5% of average estimation error).
https://www.bsc.es/research-and-development/publications/methodology-full-system-power-modeling-heterogeneous-data
With the rise of containerization, as well as the established adoption of virtualization technologies, run-time power and energy management is becoming one of the key challenges in modern cloud computing. This is also fundamental as power consumption contributes to the 20% of the Total Cost of Ownership of a datacenter and energy costs will exceed hardware costs in the near future. In this context, several goals towards power optimization can be achieved. On the one hand, power capping can be enforced and on top of that the system should be able to maximize performance. On the other hand, when performance are critical, the system should be able to provide a minimum SLA and optimize power consumption without violating it. Within this context, we propose a common autonomic methodology based on the ODA control loop for containers and virtual machines. The proposed methodology is able to achieve 25% power savings for containers and can improve performance under a power cap for virtual machines.
Approximation techniques used for general purpose algorithmsSabidur Rahman
Survey on approximation techniques used for general purpose algorithms, data parallel applications ans solid-state memories. It is interesting to see how approximation algorithms can contribute to solve real-life problems with better efficiency and lower cost!
Questions? krahman@ucdavis.edu.
Simulation of Heterogeneous Cloud InfrastructuresCloudLightning
During the last years, except from the traditional CPU based hardware servers, hardware accelerators are widely used in various HPC application areas. More specifically, Graphics Processing Units (GPUs), Many Integrated Cores (MICs) and Field-Programmable Gate Arrays (FPGAs) have shown a great potential in HPC and have been widely mobilised in supercomputing and in HPC-Clouds. This presentation focuses on the development of a cloud simulation framework that supports hardware accelerators. The design and implementation of the framework are also discussed.
This presentation was given by Dr. Konstantinos Giannoutakis (CERTH) at the CloudLightning Conference on 11th April 2017.
[EWiLi2016] Enabling power-awareness for the Xen HypervisorMatteo Ferroni
Virtualization allows simultaneous execution of multi-tenant workloads on the same platform, either a server or an embedded system. Unfortunately, it is non-trivial to attribute hardware events to multiple virtual tenants, as some system’s metrics relate to the whole system (e.g., RAPL energy counters). Virtualized environments have then a rather incomplete picture of how tenants use the hardware, limiting their optimization capabilities. Thus, we propose XeMPower, a lightweight monitoring solution for Xen that precisely accounts hardware events to guest workloads. It also enables attribution of CPU power consumption to individual tenants. We show that XeMPower introduces negligible overhead in power consumption, aiming to be a reference design for power-aware virtualized environments.
Full paper: http://ceur-ws.org/Vol-1697/EWiLi16_10.pdf
Similar to An application classification guided cache tuning heuristic for (20)
TOP 10 B TECH COLLEGES IN JAIPUR 2024.pptxnikitacareer3
Looking for the best engineering colleges in Jaipur for 2024?
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We have compiled the most important slides from each speaker's presentation. This year’s compilation, available for free, captures the key insights and contributions shared during the DfMAy 2024 conference.
6th International Conference on Machine Learning & Applications (CMLA 2024)ClaraZara1
6th International Conference on Machine Learning & Applications (CMLA 2024) will provide an excellent international forum for sharing knowledge and results in theory, methodology and applications of on Machine Learning & Applications.
KuberTENes Birthday Bash Guadalajara - K8sGPT first impressionsVictor Morales
K8sGPT is a tool that analyzes and diagnoses Kubernetes clusters. This presentation was used to share the requirements and dependencies to deploy K8sGPT in a local environment.
ACEP Magazine edition 4th launched on 05.06.2024Rahul
This document provides information about the third edition of the magazine "Sthapatya" published by the Association of Civil Engineers (Practicing) Aurangabad. It includes messages from current and past presidents of ACEP, memories and photos from past ACEP events, information on life time achievement awards given by ACEP, and a technical article on concrete maintenance, repairs and strengthening. The document highlights activities of ACEP and provides a technical educational article for members.
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A review on techniques and modelling methodologies used for checking electrom...nooriasukmaningtyas
The proper function of the integrated circuit (IC) in an inhibiting electromagnetic environment has always been a serious concern throughout the decades of revolution in the world of electronics, from disjunct devices to today’s integrated circuit technology, where billions of transistors are combined on a single chip. The automotive industry and smart vehicles in particular, are confronting design issues such as being prone to electromagnetic interference (EMI). Electronic control devices calculate incorrect outputs because of EMI and sensors give misleading values which can prove fatal in case of automotives. In this paper, the authors have non exhaustively tried to review research work concerned with the investigation of EMI in ICs and prediction of this EMI using various modelling methodologies and measurement setups.
4. Introduction(cont.)
• Multi Core:-
• In multi core architecture single computing component with two or more independent
actual processing units (called "cores").
• Run multiple instructions of a program at the same time, increasing overall speed for
programs –”Parallel Computing”.
5. Muti-Core System Optimization
•Previous multi-core cache optimizations only focused on improving performance(such
as number of Hits, misses, and write backs).
•But now multi-core optimizations focused on reducing energy consumption via tuning
individual cores.
•Definition of Multi-core system optimization
• Multi-core system optimization improve system performance and energy
consumption by tuning the system to the application’s runtime behavior and
resource requirements.
6. What is Cache Tuning?
•Cache tuning the task of choosing the best configuration of cache design parameters
for a particular application, or for a particular phase of an application, such that
performance, power and/or energy are optimized.
7. Cache Tuning Process
Step 1:- Execute the application for one tuning interval in each potential
configuration (tuning intervals must be long enough for the cache behavior to
stabilize).
Step 2:- Gather cache statistics, such as the number of accesses, misses, and
write backs, for each explored configuration.
Step 3:- Combine the cache statistics with an energy model to determine the
optimal cache configuration.
Step 4:- Fix the cache parameter values to the optimal cache configuration’s
parameter values.
9. Multi-core Architectural Layout(cont.)
• Multi- core Architecture consist of:-
1. Arbitrary number of cores
2. A cache tuner
• Each core has a private data cache (L1).
• Global cache tuner connected to each core’s private data cache(L1).
• It calculates the cache tuner heuristics by gathering cache statistics, coordinating
cache tuning among the cores and calculates the cache’s energy consumption.
10. Multi-core Architectural Layout(cont.)
Overheads in this Multi-core Architecture Layout
• During tuning, applications incur stall cycles while the tuner gathers cache statistics,
calculates energy consumption, and changes the cache configuration.
• These tuning stall cycles introduce Energy and Performance overhead.
• Our tuning heuristic considers these overheads incurred during the tuning stall cycles,
and thus minimizes the number of simultaneously tuned cores and the tuning energy
and performance overheads.
12. Multi-core Architectural Layout(cont.)
• Figure illustrates the similarities using actual data cache miss rates for an 8-core system
(the cores are denoted as P0 to P7).
•We evaluate cache miss rate similarity by normalizing the caches’ miss rates to the core
with the lowest miss rate.
•In first figure, normalized miss rates are nearly 1.0 for all cores, all caches are classified
as having similar behavior.
•In second figure, normalized miss rates show that P1 has similar cache behavior as P2 to
P7 (i.e. P1 to P7’s normalized miss rates are nearly 3.5), but P0 has different cache
behavior than P1 to P7.
13. Application Classification Guided Cache
Tuning Heuristic
• Application classification is based on the two things :-
1. Cache Behaviour
2. Data Sharing or Non Data Sharing Application
• Cache accesses and misses are used to determine if data sets have similar cache
behavior.
•In data-sharing application’s if coherence misses attribute to more than 5% of the total
cache misses , then application is classified as data sharing otherwise the application is
non-data-sharing.
15. Application Classification Guided Cache
Tuning Heuristic(cont.)
• Application classification guided cache tuning heuristic, which consists of three
main steps:
1) Application profiling and initial tuning
2) Application classification
3) Final tuning actions
16. Application Classification Guided Cache
Tuning Heuristic(cont.)
•Step 1 profiles the application to gather the caches statistics, which are used to determine
cache behavior and data sharing in step 2.
•Step 1 is critical for avoiding redundant cache tuning in situations where the data sets have
similar cache behavior and similar optimal configurations.
•Condition 1 and Condition 2 classify the applications based on whether or not the cores have
similar cache behavior and/or exhibit data sharing, respectively.
•Evaluating these conditions determines the necessary cache tuning effort in Step 3.
•If condition 1 is evaluated as true. In these situations, only a single cache needs to be tuned.
•When final configuration is obtained apply this configuration to all other cores.
17. Application Classification Guided Cache
Tuning Heuristic(cont.)
•If the data sets have different cache behavior, or Condition 1 is false, tuning is
more complex and several cores must be tuned.
•If the application does not shares data, or Condition 2 is false, the heuristic only
tunes one core from each group and cores can be tuned independently without
affecting the behavior of the other cores.
•If the application shares data, or Condition 2 is true, the heuristic still only tunes
one core from each group but the tuning must be coordinated among the cores.
18. Experimental Results
• We quantified the energy savings and performance of our heuristic using SPLASH-2
multithreaded application.
• The SPLASH-2 suite is one of the most widely used collections of multithreaded
workloads.
• On the SESC simulator for a 1-, 2-, 4-, 8- and 16- core system. In SESC, we modeled a
heterogeneous system with the L1 data cache parameters.
•Since the L1 data cache has 36 possible configurations, our design space is 36^n where
n is the of cores in the system.
•The L1 instruction cache and L2 unified cache were fixed at the base configuration and
256 KB, 4-way set associative cache with a 64 byte line size, respectively. We modified
SESC to identify coherence misses.
19. Experimental Results(cont.)
Energy Model for the multi-core system
• total energy = ∑(energy consumed by each core)
• energy consumed by each core:
energy = dynamic_energy + static_energy + fill_energy + writeback_energy + CPU_stall_energy
• dynamic_energy: The dynamic power consumption originates from logic-gate activities in the
CPU.
dynamic_energy = dL1_accesses * dL1_access_energy
• static energy: The static energy consumption enables energy-aware software development.
Static energy is actually not good for the system at all.
static_energy = ((dL1_misses * miss_latency_cycles) + (dL1_hits * hit_latency_cycles) +
(dL1_writebacks * writeback_latency_cycles)) * dL1_static_energy
20. Experimental Results(cont.)
•fill_energy: fill_energy = dL1_misses * (linesize / wordsize) *mem_read_energy_perword
• writeback_energy: Write back is a storage method in which data is written into the cache
writeback_energy = dL1_writebacks * (linesize / wordsize) *
mem_write_energy_perword
•CPU_stall_energy: CPU_stall_energy = ((dL1_misses * miss_latency_cycles) +
(dL1_writebacks * writeback_latency_cycles)) * CPU_idle_energy
• Our model calculates the dynamic and static energy of each data cache, the energy needed to
fill the cache on a miss, the energy consumed on a cache write back, and the energy consumed
when the processor is stalled during cache fills and write backs.
• We gathered dL1_misses, dL1_hits, and dL1_writebacks cache statistics using SESC.
21. Experimental Results(cont.)
• We assumed the core’s idle energy (CPU_idle_energy) to be 25% and the static energy
per cycle to be 25% of the cache’s dynamic energy.
• Let the tuning interval of 50,000 cycles.
• Using configuration_energy_per_cycle to determine the energy consumed during each
500,000 cycle tuning interval and the energy consumed in the final configuration.
• Energy savings were calculated by normalizing the energy to the energy consumed
executing the application in the base configuration.
22. Results and Analysis
•Figure given below depict the energy savings and performance, respectively, for the
optimal configuration determined via exhaustive design space exploration (optimal) for 2-
and 4-core systems and for the final configuration found by our application classification
cache tuning heuristic (heuristic) for 2-, 4-, 8-, and 16-core systems, for each application
and averaged across all applications (Avg).
•Our heuristic achieved 26% and 25% energy savings, incurred 9% and 6% performance
penalties, and achieved average speedups for the 8- and 16-core systems, respectively.
23. Results and Analysis(Cont..)
• Normalised performance for the optimal cache (optimal) for 2- and 4-core systems and
the final configuration for the application classification cache tuning heuristic for 2-, 4-,
8- and 16-core systems as compared to the systems respective base configurations.
25. Conclusion
•Our heuristic classified applications based on data sharing and cache behavior, and used
this classification to identify which cores needed to be tuned and to reduce the number
of cores being tuned simultaneously.
26. Future Work
•Our heuristic searched at most 1% of the design space, yielded configurations within 2%
of the optimal, and achieved an average of 25% energy savings.
•In future work we plan to investigate how our heuristic will be applicable to a larger
system with hundreds of cores.